CY7C64113C-PVXC Cypress Semiconductor Corp, CY7C64113C-PVXC Datasheet - Page 34

• Manufacturer Part Number: CY7C64113C-PVXC
• Description: IC MCU 8K FULL SPEED USB 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64113C-PVXC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C641xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 36
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 4 : ACK
Bits[6..5] : Reserved
Bit 7 : STALL
mode bits are set to ACK-IN, and the SIE stalls an IN packet if
Table 37. USB Endpoint Counter Registers
Bits[5..0] : Byte Count
Bit 6 : Data Valid
Bit 7 : Data 0/1 Toggle
Whenever the count updates from a SETUP or OUT transaction
on endpoint 0, the counter register locks and cannot be written
by the CPU. Reading the register unlocks it. This prevents
firmware from overwriting a status update on incoming SETUP
or OUT transactions before firmware has a chance to read the
data. Only endpoint 0 counter register is locked when updated.
The locking mechanism does not apply to the count registers of
other endpoints.
Document Number: 38-08001 Rev. *D
USB Endpoint
Counter
Bit #
Bit Name
Read/Write
Reset
This bit is set whenever the SIE engages in a transaction
to the register’s endpoint that completes with an ACK
packet.
Must be written zero during register writes.
These counter bits indicate the number of data bytes in a
transaction. For IN transactions, firmware loads the count
with the number of bytes to be transmitted to the host from
the endpoint FIFO. Valid values are 0 to 32, inclusive. For
OUT or SETUP transactions, the count is updated by
hardware to the number of data bytes received, plus 2 for
the CRC bytes. Valid values are 2 to 34, inclusive.
This bit is set on receiving a proper CRC when the
endpoint FIFO buffer is loaded with data during
transactions. This bit is used OUT and SETUP tokens only.
If the CRC is not correct, the endpoint interrupt occurs, but
Data Valid is cleared to a zero.
This bit selects the DATA packet’s toggle state: 0 for
DATA0, 1 for DATA1. For IN transactions, firmware must
set this bit to the desired state. For OUT or SETUP
transactions, the hardware sets this bit to the state of the
received Data Toggle bit.
If this STALL is set, the SIE stalls an OUT packet if the
Data 0/1 Toggle
R/W
7
0
Data Valid
R/W
6
0
Byte Count Bit 5 Byte Count Bit 4 Byte Count Bit 3 Byte Count Bit 2 Byte Count Bit 1 Byte Count Bit 0
R/W
5
0
R/W
4
0
the mode bits are set to ACK-OUT. For all other modes, the
STALL bit must be a LOW.
USB Endpoint Counter Registers
There are five Endpoint Counter registers, with identical formats
for both control and non-control endpoints. These registers
contain byte count information for USB transactions, as well as
bits for data packet status. The format of these registers is shown
in
Endpoint Mode/Count Registers Update and Locking
Mechanism
The contents of the endpoint mode and counter registers are
updated, based on the packet flow diagram in
points, UPDATE and SETUP, are shown in the same figure. The
following activities occur at each time point:
SETUP:
The SETUP bit of the endpoint 0 mode register is forced HIGH
at this time. This bit is forced HIGH by the SIE until the end of the
data phase of a control write transfer. The SETUP bit can not be
cleared by firmware during this time.
The affected mode and counter registers of endpoint 0 are
locked from any CPU writes once they are updated. These
registers can be unlocked by a CPU read, only if the read
operation occurs after the UPDATE. The firmware needs to
perform a register read as a part of the endpoint ISR processing
to unlock the effected registers. The locking mechanism on
mode and counter registers ensures that the firmware
recognizes the changes that the SIE might have made since the
previous IO read of that register.
UPDATE:
1. Endpoint Mode Register – All the bits are updated (except the
2. Counter Registers – All bits are updated.
3. Interrupt – If an interrupt is to be generated as a result of the
4. The contents of the updated endpoint 0 mode and counter
Table
SETUP bit of the endpoint 0 mode register).
transaction, the interrupt flag for the corresponding endpoint
is set at this time. For details on what conditions are required
to generate an endpoint interrupt, refer to
registers are locked, except the SETUP bit of the endpoint 0
mode register which was locked earlier.
R/W
37:
3
0
ADDRESSES
R/W
2
0
0x11, 0x13, 0x15, 0x41, 0x43
R/W
1
0
CY7C64013C
CY7C64113C
Table
Figure
Page 34 of 53
R/W
39.
0
0
9. Two time
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