CY7C64113C-PVXC Cypress Semiconductor Corp, CY7C64113C-PVXC Datasheet - Page 33

• Manufacturer Part Number: CY7C64113C-PVXC
• Description: IC MCU 8K FULL SPEED USB 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64113C-PVXC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C641xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 36
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Endpoint 0 is bidirectional to both receive and transmit data. The
other endpoints are unidirectional, but selectable by the user as
IN or OUT endpoints.
Table 35. USB Device Endpoint Zero Mode Registers
Bits[3..0] : Mode
Bit 4 : ACK
Bit 5: Endpoint 0 OUT Received
Bit 6: Endpoint 0 IN Received
Bit 7: Endpoint 0 SETUP Received
Table 36. USB Non-Control Device Endpoint Mode Registers
Bits[3..0] : Mode
Document Number: 38-08001 Rev. *D
USB Device
Endpoint Zero
Mode
Bit #
Bit Name
Read/Write
Reset
USB
Non-Control
Device
Endpoint
Mode
Bit #
Bit Name
Read/Write
Reset
These sets the mode which control how the control end-
point responds to traffic.
This bit is set whenever the SIE engages in a transaction
to the register’s endpoint that completes with an ACK
packet.
1 = Token received is an OUT token. 0 = Token received
is not an OUT token. This bit is set by the SIE to report the
type of token received by the corresponding device
address is an OUT token. The bit must be cleared by
firmware as part of the USB processing.
1= Token received is an IN token. 0= Token received is not
an IN token. This bit is set by the SIE to report the type of
token received by the corresponding device address is an
IN token. The bit must be cleared by firmware as part of
the USB processing.
1= Token received is a SETUP token. 0= Token received
is not a SETUP token. This bit is set ONLY by the SIE to
report the type of token received by the corresponding
device address is a SETUP token. Any write to this bit by
the CPU will clear it (set it to 0). The bit is forced HIGH from
the start of the data packet phase of the SETUP
transaction until the start of the ACK packet returned by
Endpoint 0 SETUP
Received
STALL
R/W
R/W
7
0
7
0
Reserved
Endpoint 0 IN
Received
R/W
6
0
R/W
6
0
Endpoint 0 OUT
Reserved
Received
R/W
5
0
R/W
5
0
ACK
R/W
4
0
ACK
R/W
4
0
The endpoint mode register is cleared during reset. The endpoint
zero EPA0 mode register uses the format shown in
Bits[6:0] of the endpoint 0 mode register are locked from CPU
write operations whenever the SIE has updated one of these bits,
which the SIE does only at the end of the token phase of a
transaction (SETUP... Data... ACK, OUT... Data... ACK, or IN...
Data... ACK).
subsequent read of this register. Only endpoint 0 mode registers
are locked when updated. The locking mechanism does not
apply to the mode registers of other endpoints.
Because of these hardware locking features, firmware must
perform an IORD after an IOWR to an endpoint 0 register. This
verifies that the contents have changed as desired, and that the
SIE has not updated these values.
While the SETUP bit is set, the CPU cannot write to the endpoint
zero FIFOs. This prevents firmware from overwriting an incoming
SETUP transaction before firmware has a chance to read the
SETUP data. Refer to
memory locations.
The Mode bits (bits [3:0]) control how the endpoint responds to
USB bus traffic. The mode bit encoding is shown
Additional information on the mode bits can be found
USB Non-Control Endpoint Mode Registers
The format of the non-control endpoint mode register is shown
in
Table
Mode Bit 3
the SIE. The CPU should not clear this bit during this
interval, and subsequently, until the CPU first does an
IORD to this endpoint 0 mode register. The bit must be
cleared by firmware as part of the USB processing.
These sets the mode which control how the control end-
point responds to traffic. The mode bit encoding is shown
in
Mode Bit 3
R/W
36.
Table 38
3
0
R/W
3
0
The CPU can unlock these bits by doing a
Mode Bit 2
Mode Bit 2
R/W
Table 34
R/W
2
0
2
0
ADDRESSES 0x14, 0x16, 0x42
for the appropriate endpoint zero
Mode Bit 1
Mode Bit 1
R/W
R/W
1
0
1
0
ADDRESSES
CY7C64013C
CY7C64113C
Mode Bit 0
Mode Bit 0
Page 33 of 53
R/W
R/W
0
0
0
0
Table
inTable
inTable
,
0x12
0x44
35.
38.
39.
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