CY7C63001C-SXCT Cypress Semiconductor Corp, CY7C63001C-SXCT Datasheet - Page 11

• Manufacturer Part Number: CY7C63001C-SXCT
• Description: IC MCU 4K USB MCU LS 20SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63001C-SXCT

• Applications: USB Microcontroller
• Core Processor: M8A
• Program Memory Type: OTP (4 kB)
• Controller Series: CY7C630xx
• Ram Size: 128 x 8
• Interface: USB
• Number Of I /o: 12
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08026 Rev. *B
6.7
The XTALIN and XTALOUT pins support connection of a
6-MHz ceramic resonator. The feedback capacitors and bias
resistor are internal to the IC, as shown in Figure 2 Leave
XTALOUT unconnected when driving XTALIN from an external
oscillator.
6.8
Interrupts are generated by the General Purpose I/O lines, the
Cext pin, the internal timer, and the USB engine. All interrupts
are maskable by the Global Interrupt Enable Register. Access
to this register is accomplished via IORD, IOWR, and IOWX
instructions to address 0x20. Writing a “1” to a bit position
enables the interrupt associated with that position. During a
reset, the contents of the Interrupt Enable Register are
cleared, disabling all interrupts. Figure 6-13 illustrates the
format of the Global Interrupt Enable Register.
CEXTIE
R/W
b7
0
XTALIN/XTALOUT
Interrupts
Acknowledge
(to Microcontroller)
Interrupt
(to USB SIE)
Interrupt
Register
Enable
Global
CLR
clk1x
clk2x
GPIOIE
R/W
b6
0
Figure 6-13. Global Interrupt Enable Register (GIER - Address 0x20)
Enable [7:0]
Interrupt
Interrupt
Logic 1
128-
GPIO
Logic 1
Logic 1
CEXT
Reserved
µ
Doubler
s
Figure 3. Interrupt Controller Logic Block Diagram
Clock
b5
0
Figure 2. Clock Oscillator On-chip Circuit
D
D
CLK
D
CLK
CLK
CLR
CLR
CLR
Q
Q
Q
30 pF
Enable [1]
Enable [6]
Enable [7]
EP1IE
R/W
b4
0
The interrupt controller contains a separate latch for each
interrupt. See Figure 3 for the logic block diagram for the
interrupt controller. When an interrupt is generated, it is
latched as a pending interrupt. It stays as a pending interrupt
until it is serviced or a reset occurs. A pending interrupt only
generates an interrupt request if it is enabled in the Global
Interrupt Enable Register. The highest priority interrupt
request is serviced following the execution of the current
instruction.
When servicing an interrupt, the hardware first disables all
interrupts by clearing the Global Interrupt Enable Register.
Next, the interrupt latch of the current interrupt is cleared. This
is followed by a CALL instruction to the ROM address
associated with the interrupt being serviced (i.e., the interrupt
vector). The instruction in the interrupt table is typically a JMP
instruction to the address of the Interrupt Service Routine
(ISR). The user can re-enable interrupts in the interrupt service
routine by writing to the appropriate bits in the Global Interrupt
Enable Register. Interrupts can be nested to a level limited
only by the available stack space.
EP0IE
R/W
b3
0
30 pF
Wake-up CLR
128-
128-
1-ms CLR
1-ms IRQ
End P0 CLR
End P0 IRQ
End P1 CLR
End P1 IRQ
GPIO CLR
GPIO IRQ
Wake-up IRQ
1024IE
R/W
µ
µ
b2
0
s CLR
s IRQ
Interrupt
Encoder
Priority
XTALOUT
XTALIN
Interrupt
Vector
128IE
R/W
IRQ
b1
0
CY7C63001C
CY7C63101C
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Reserved
b0
0