CY7C64714-100AXC Cypress Semiconductor Corp, CY7C64714-100AXC Datasheet - Page 39

• Manufacturer Part Number: CY7C64714-100AXC
• Description: IC MCU USB EZ FX1 16KB 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64714-100AXC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

configured to operate in auto mode and it is desired to send
two packets back to back:
In this particular scenario, the developer must make sure to
assert PKTEND at least one clock cycle after the rising edge
that caused the last byte/word to be clocked into the previous
auto committed packet. Figure 10-12 below shows this
scenario. X is the value the AUTOINLEN register is set to
when the IN endpoint is configured to be in auto mode.
10.12
Table 10-14. Slave FIFO Asynchronous Packet End Strobe Parameters
Document #: 38-08039 Rev. *C
PKTEND
t
t
t
FIFOADR
IFCLK
SLWR
DATA
• A full packet (full defined as the number of bytes in the FIFO
• A short one byte/word packet committed manually using the
PEpwl
PWpwh
XFLG
meeting the level set in AUTOINLEN register) committed
automatically followed by
PKTEND pin.
Parameter
Slave FIFO Asynchronous Packet End Strobe
Figure 10-12. Slave FIFO Synchronous Write Sequence and Timing Diagram
Figure 10-13. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
PKTEND Pulse Width LOW
PKTEND Pulse Width HIGH
PKTEND to FLAGS Output Propagation Delay
t
SFA
t
IFCLK
>= t
t
SFD
SWR
X-4
PKTEND
FLAGS
t
FDH
Description
t
SFD
X-3
t
FDH
t
SFD
X-2
t
PEpwl
t
XFLG
t
FDH
Figure 10-12 shows a scenario where two packets are being
committed. The first packet gets committed automatically
when the number of bytes in the FIFO reaches X (value set in
AUTOINLEN register) and the second one byte/word short
packet being committed manually using PKTEND. Note that
there is at least one IFCLK cycle timing between asserting
PKTEND and clocking of the last byte of the previous packet
(causing the packet to be committed automatically). Failing to
adhere to this timing, will result in the FX2 failing to send the
one byte/word short packet.
t
SFD
X-1
t
[20]
PEpwh
t
FDH
Min.
50
50
t
SFD
X
t
FDH
At least one IFCLK cycle
t
SFD
Max.
115
1
[17]
CY7C64713/14
>= t
t
FDH
WRH
t
t
FAH
SPE
Page 39 of 50
Unit
ns
ns
ns
t
PEH