CY7C64714-100AXC Cypress Semiconductor Corp, CY7C64714-100AXC Datasheet - Page 44

• Manufacturer Part Number: CY7C64714-100AXC
• Description: IC MCU USB EZ FX1 16KB 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64714-100AXC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.17.3 Sequence Diagram of a Single and Burst Asynchronous Read
Figure 10-21 diagrams the timing relationship of the SLAVE
FIFO signals during an asynchronous FIFO read. It shows a
single read followed by a burst read.
Document #: 38-08039 Rev. *C
FLAGS
FIFOADR
FIFO DATA BUS Not Driven
FIFO POINTER
• At t = 0 the FIFO address is stable and the SLCS signal is
• At t = 1, SLOE is asserted. This results in the data bus being
• At t = 2, SLRD is asserted. The SLRD must meet the
SLRD
SLCS
DATA
SLOE
asserted.
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
minimum active pulse of t
pulse width of t
in asserted with SLRD or before SLRD is asserted. (i.e., the
SLCS and SLRD signals must both be asserted to start a
valid read condition.)
t=0
t=1
RDpwh
N
Driven
Data (X)
Figure 10-21. Slave FIFO Asynchronous Read Sequence and Timing Diagram
t
SFA
t
OEon
Figure 10-22. Slave FIFO Asynchronous Read Sequence of Events Diagram
SLOE
. If SLCS is used then, SLCS must be
t=2
t
RDpwl
RDpwl
Driven: X
t
XFD
t=3
N
N
t=4
t
RDpwh
and minimum de-active
t
FAH
SLRD
t
t
OEoff
XFLG
N
N
SLRD
T=0
N+1
T=1
N
SLOE
t
t
SFA
OEon
N
T=2
Not Driven
N+1
t
RDpwl
t
XFD
T=3
SLOE
The same sequence of events is also shown for a burst read
marked with T = 0 through 5. Note: In burst read mode, during
SLOE is assertion, the data bus is in a driven state and outputs
the previous data. Once SLRD is asserted, the data from the
FIFO is driven on the data bus (SLOE must also be asserted)
and then the FIFO pointer is incremented.
• The data that will be driven, after asserting SLRD, is the
t
N+1
RDpwh
updated data from the FIFO. This data is valid after a propa-
gation delay of t
Figure 10-21, data N is the first valid data read from the
FIFO. For data to appear on the data bus during the read
cycle (i.e. SLRD is asserted), SLOE MUST be in an asserted
state. SLRD and SLOE can also be tied together.
N+1
N
T=4
SLRD
t
RDpwl
t
XFD
N+1
T=5
N+1
SLRD
t
N+2
RDpwh
XFD
N+2
T=6
N+1
from the activating edge of SLRD. In
SLRD
t
RDpwl
t
XFD
N+3
N+2
N+2
T=7
t
t
RDpwh
FAH
SLRD
t
OEoff
CY7C64713/14
t
XFLG
N+3
N+2
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SLOE
Not Driven
N+3