Z84C0010PEG Zilog, Z84C0010PEG Datasheet - Page 292
Z84C0010PEG
Manufacturer Part Number
Z84C0010PEG
Description
IC 10MHZ Z80 CMOS CPU 40-DIP
Manufacturer
Zilog
Series
Z80r
Specifications of Z84C0010PEG
Processor Type
Z80
Features
Enhanced Z80 Microprocessor/CPU
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Operating Temperature Range
-40°C To +100°C
Svhc
No SVHC (18-Jun-2010)
Operating Temperature Max
100°C
Rohs Compliant
Yes
Processor Series
Z84C0xx
Core
Z80
Data Bus Width
8 bit
Program Memory Size
64 KB
Maximum Clock Frequency
10 MHz
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Base Number
84
Clock Frequency
10MHz
Frequency Typ
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3898
Z84C0010PEG
Z84C0010PEG
Available stocks
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Manufacturer
Quantity
Price
Company:
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Manufacturer:
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Quantity:
110
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Operation:
Op Code:
Description: The contents of register C are placed on the bottom half (A0 through A7) of
Condition Bits Affected:
Example:
UM008005-0205
Z80 CPU
User’s Manual
(HL) ← (C), B ← B -1, HL ← HL + 1
INI
the address bus to select the I/O device at one of 256 possible ports.
Register B may be used as a byte counter, and its contents are placed on the
top half (A8 through A15) of the address bus at this time. Then one byte
from the selected port is placed on the data bus and written to the CPU. The
contents of the HL register pair are then placed on the address bus and the
input byte is written to the corresponding location of memory. Finally, the
byte counter is decremented and register pair HL is incremented.
S is unknown
Z is set if B–1 = 0, reset otherwise
H is unknown
P/V is unknown
N is set
C is not affected
If the contents of register C are
contents of the HL register pair are
peripheral device mapped to I /O port address
memory location
1001H
1
1
1
0
, and register B contains
M Cycles
1
1
4
0
0
1000H
1
0
contains
16 (4, 5, 3, 4)
1
0
INI
T States
07H
0
1
0FH
7BH
1000H
, the contents of register B are
.
1
0
, the HL register pair contains
ED
A2
, and byte
07H
4 MHz E.T.
. At execution of
4.00
7BH
Z80 Instruction Set
is available at the
10H
INI
, the
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