Z84C0010PEG Zilog, Z84C0010PEG Datasheet - Page 43
Z84C0010PEG
Manufacturer Part Number
Z84C0010PEG
Description
IC 10MHZ Z80 CMOS CPU 40-DIP
Manufacturer
Zilog
Series
Z80r
Specifications of Z84C0010PEG
Processor Type
Z80
Features
Enhanced Z80 Microprocessor/CPU
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Operating Temperature Range
-40°C To +100°C
Svhc
No SVHC (18-Jun-2010)
Operating Temperature Max
100°C
Rohs Compliant
Yes
Processor Series
Z84C0xx
Core
Z80
Data Bus Width
8 bit
Program Memory Size
64 KB
Maximum Clock Frequency
10 MHz
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Base Number
84
Clock Frequency
10MHz
Frequency Typ
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3898
Z84C0010PEG
Z84C0010PEG
Available stocks
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Manufacturer
Quantity
Price
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Manufacturer:
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UM008005-0205
Action
CPU Reset
A CPU reset forces both the IFF1 and IFF2 to the reset state, which disables
interrupts. Interrupts can be enabled at any time by an EI instruction from
the programmer. When an EI instruction is executed, any pending interrupt
request is not accepted until after the instruction following EI is executed.
This single instruction delay is necessary when the next instruction is a
return instruction. Interrupts are not allowed until a return is completed. The
EI instruction sets both IFF1 and IFF2 to the enable state. When the CPU
accepts a maskable interrupt, both IFF1 and IFF2 are automatically reset,
inhibiting further interrupts until the programmer issues a new El
instruction. Note that for all of the previous cases, IFF1 and IFF2 are always
equal.
The purpose of IFF2 is to save the status of IFF1 when a non-maskable
interrupt occurs. When a non-maskable interrupt is accepted, IFF1 resets to
prevent further interrupts until reenabled by the programmer. Thus, after a
non-maskable interrupt is accepted, maskable interrupts are disabled but the
previous state of IFF1 has been saved so that the complete state of the CPU
just prior to the non-maskable interrupt can be restored at any time. When a
Load Register A with Register I
Register A with Register R
of IFF2 is copied to the parity flag where it can be tested or stored.
A second method of restoring the status of IFF1 is through the execution of
a
instruction indicates that the non-maskable interrupt service routine is
complete and the contents of IFF2 are now copied back into IFF1 so that the
status of IFF1 just prior to the acceptance of the non-maskable interrupt is
restored automatically.
Table 2 is a summary of the effect of different instructions on the two enable
flip-flops.
Table 2. Interrupt Enable/Disable, Flip-Flops
Return From Non
-
Maskable Interrupt
IFF1 IFF2 Comments
0
0
(
LD A
,
Maskable Interrupt, INT Disabled
(
R
LD A
) instruction is executed, the state
,
I
(RETN) instruction. This
) instruction or a
User’s Manual
Z80 CPU
Load
Overview
23
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