Z84C0010PEG Zilog, Z84C0010PEG Datasheet - Page 79

• Manufacturer Part Number: Z84C0010PEG
• Description: IC 10MHZ Z80 CMOS CPU 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C0010PEG

• Processor Type: Z80
• Features: Enhanced Z80 Microprocessor/CPU
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Operating Temperature Range: -40°C To +100°C
• Svhc: No SVHC (18-Jun-2010)
• Operating Temperature Max: 100°C
• Rohs Compliant: Yes
• Processor Series: Z84C0xx
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Base Number: 84
• Clock Frequency: 10MHz
• Frequency Typ: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3898; Z84C0010PEG

UM008005-0205
Address A
(
specified 8-bit operation is performed between the data in the
accumulator and the source data. The result of the operation is placed in
the accumulator with the exception of compare (
accumulator unchanged. All these operations effect the flag register as a
result of the specified operation.
register or a memory location as both source and destination of the result.
When the source operand is addressed using the index registers, the
displacement must follow directly. With immediate addressing, the actual
operand follows directly. For example, the instruction
Assuming that the accumulator contained the value F3H, the result of
is placed in the accumulator:
The Add instruction (
source location and the data in the accumulator. The Subtract (
performs a binary subtraction. When the Add with Carry is specified,
(
or subtracted respectively. The flags and decimal adjust instruction (
in the Z80 allow arithmetic operations for:
•
•
•
Other instructions in this group are logical and (
exclusive or (
DEC
ADC
A+1
Multiprecision packed BCD numbers
Multiprecision signed or unsigned binary numbers
Multiprecision two’s complement signed numbers
) instructions. In all these instructions, except
) or the Subtract with Carry (
Accumulator before operation
Operand
Result to Accumulator
E6
07
XOR
Operand
Op Code
), and compare (
ADD
0000 0111
) performs a binary add between the data in the
0000 0011
INC
SBC
CP
).
=
and
), then the Carry flag is also added
1111 0011
07H
Z80 CPU Instruction Description
DEC
=
03H
instructions specify a
AND
CP
INC
) that leaves the
=
), logical or (
F3H
AND 07H
and
User’s Manual
DEC
Z80 CPU
SUB
, the
OR
is:
)
),
DAA
03H
)
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