MPC855TVR50D4 Freescale Semiconductor, MPC855TVR50D4 Datasheet - Page 2

• Manufacturer Part Number: MPC855TVR50D4
• Description: IC MPU POWERQUICC 50MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC Ir

Specifications of MPC855TVR50D4

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 8KB
• Cpu Speed: 50MHz
• Embedded Interface Type: Ethernet, I2C, SPI, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 357
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MPC855T Key Features
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— Large on-chip transmit and receive FIFOs to support a variety of bus latencies
— Retransmission from transmit FIFO following a collision
— Automatic internal flushing of the receive FIFO for runts and collisions
— Off-chip buffer descriptor rings of user-definable size that allow nearly unlimited flexibility in
10/100-Mbps media access control (MAC) features
— Address recognition
— Full support of the media-independent interface
— Interrupt modes
— Automatic interrupt vector generation for receive and transmit events
— Ethernet channel bursts data to/from external memory
ATM support
— Compliant with ATM forum UNI 4.0 specification
— Cell processing up to 50–70 Mbps at 50-MHz system clock
— Cell multiplexing/demultiplexing
— Support of AAL5 and AAL0 protocols on a per-VC basis
— ATM pace control (APC) scheduler, providing:
— Support for two types of physical interfaces
— UTOPIA-mode ATM supports:
— Serial-mode ATM connection supports:
above)
management of transmit and receive buffer memory
– Broadcast
– Single station address
– Promiscuous mode
– Multicast hashing
– Per-frame
– Per-buffer (selectable buffer interrupt functionality using the I bit is not supported)
Categories: transmit interrupt, receive interrupt, non-time critical interrupt
– AAL0 support enables OAM and software implementation of other protocols)
– Direct support of constant bit rate (CBR)
– Direct support of unspecified bit rate (UBR)
– Control mechanisms enabling software support of available bit rate (ABR)
– UTOPIA (10/100-Mbps is not supported with this interface)
– Byte-aligned serial (e.g. T1/E1/ADSL)
– UTOPIA level 1 master with cell-level handshake
– Multi-PHY (up to 4 physical layer devices)
– Connection to 25 Mbps, 51 Mbps, or 155 Mbps framers
– UTOPIA clock rates of 1:2 or 1:3 system clock rates
MPC855T Communications Controller Technical Summary
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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