MPC855TVR50D4 Freescale Semiconductor, MPC855TVR50D4 Datasheet - Page 7

• Manufacturer Part Number: MPC855TVR50D4
• Description: IC MPU POWERQUICC 50MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC Ir

Specifications of MPC855TVR50D4

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 8KB
• Cpu Speed: 50MHz
• Embedded Interface Type: Ethernet, I2C, SPI, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 357
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1.2
The MPC855T is comprised of four modules connected to the 32-bit internal bus: the embedded MPC8xx
core, the system integration unit (SIU), the communications processor module (CPM), and the Fast Ethernet
controller (FEC). The MPC855T block diagram is shown in Figure 1.
1.2.1
The embedded MPC8xx core is compliant with the PowerPC user instruction set architecture; refer to
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture for more
information. The embedded MPC8xx core is a fully-static design that consists of two functional units—the
integer unit and the load/store unit. It executes all integer and load/store operations directly on the hardware.
The core supports integer operations on a 32-bit internal data path and 32-bit arithmetic hardware. The core
interface to the internal and external buses is 32 bits. The core uses a two-instruction load/store queue, a
four- instruction prefetch queue, and a six-instruction history buffer. The core performs branch folding and
MOTOROLA
CONTROLLER
ETHERNET
EMBEDDED
MPC8XX
CORE
FAST
FIFO’S
10/100
DMA’S
MBPS
MAC
MII
— 3.3-V operation (No support for 5V I/O)
— 357-pin ball grid array (BGA) package
MPC855T Architecture Overview
Embedded MPC8xx Core
LOAD/STORE
INSTRUCTION
INTERFACE PORT
PARALLEL I / O
GENERATORS
MPC855T Communications Controller Technical Summary
BUS
BAUD RATE
BUS
PARALLEL
SCC1
Freescale Semiconductor, Inc.
TIME SLOT ASSIGNER
For More Information On This Product,
SMC1
4 KBYTE
I CACHE
D CACHE
4 KBYTE
DMMU
IMMU
Figure 1. MPC855T Block Diagram
TIMERS
SERIAL INTERFACE
TIMER
Go to: www.freescale.com
4
32-BIT RISC MICROCONTROLLER
SMC2
AND PROGRAM ROM
CONTROLLER
INTERRUPT
SPI
UNIFIED BUS
8K DUAL-PORT
I
RAM
2
C
MPC855T Architecture Overview
SYSTEM INTEGRATION UNIT
CHANNELS
CHANNELS
2 VIRTUAL
10 SERIAL
COMMUNICATIONS
DMA
IDMA
AND
MEMORY CONTROLLER
PROCESSOR
BUS INTERFACE UNIT
SYSTEM FUNCTIONS
PCMCIA INTERFACE
REAL TIME CLOCK
MODULE
7