MPC8245LVV333D Freescale Semiconductor, MPC8245LVV333D Datasheet - Page 43

• Manufacturer Part Number: MPC8245LVV333D
• Description: IC MPU 32BIT 333MHZ PPC 352-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIr

Specifications of MPC8245LVV333D

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 333MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 352-TBGA
• Processor Series: MPC8xxx
• Core: 603e
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 2 V, 2.1 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 333MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 352
• Supply Voltage Range: 1.9V To 2.2V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Notes:
1. Limited by the maximum PCI input frequency (66 MHz).
2. Limited by the maximum system memory interface operating frequency (100 MHz @ 350 MHz CPU).
3. Limited by the minimum memory VCO frequency (132 MHz).
4. Limited due to the maximum memory VCO frequency (372 MHz).
5. Limited by the maximum CPU operating frequency.
6. Limited by the minimum CPU VCO frequency (360 MHz).
7. Limited by the maximum CPU VCO frequency (Maximum marked CPU speed X 2).
8. In clock-off mode, no clocking occurs inside the MPC8245, regardless of the PCI_SYNC_IN input.
9. Range values are rounded down to the nearest whole number (decimal place accuracy removed).
10. PLL_CFG[0:4] settings not listed are reserved.
11. Multiplier ratios for this PLL_CFG[0:4] setting differ from or do not exist on the MPC8240 and are not backward-compatible.
12. PCI_SYNC_IN range for this PLL_CFG[0:4] setting differs from the MPC8240 and may not be fully backward-compatible.
13. Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.
14. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL is
15. In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral logic
16. Limited by the maximum system memory interface operating frequency (133 MHz @ 333 MHz CPU).
17. Limited by the minimum CPU operating frequency (100 MHz).
18. Limited by the minimum memory bus frequency (50 MHz).
Rev B
Rev D
Ref
1E
1E
1F
disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is for hardware modeling. The AC timing
specifications in this document do not apply in PLL bypass mode.
PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this mode, the OSC_IN input
signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation, and the processor PLL is disabled. The
PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. This mode is for hardware modeling. The AC
timing specifications in this document do not apply in dual PLL bypass mode.
CFG[0:4]
11110
11111
11110
PLL_
8
8
10,13
Table 18. PLL Configurations (333- and 350-MHz Parts) (continued)
PCI Clock
SYNC_IN)
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Range
33
(MHz)
(PCI_
Input
3
–47
1
5
333 MHz Part
Not usable
Not usable
Logic/Mem
Bus Clock
Periph
Range
66–94
(MHz)
9
231–329 33
Range
Clock
(MHz)
CPU
PCI Clock
SYNC_IN)
Range
3
(MHz)
(PCI_
Input
–50
2,5,7
1
350 MHz Part
Not usable
Not usable
Logic/Mem
Bus Clock
66–100
Periph
Range
(MHz)
9
231–350
Range
Clock
(MHz)
CPU
PCI-to-
(Mem
VCO)
Mem
2(2)
Off
Off
PLL Configurations
Multipliers
Mem-to-
3.5(2)
(CPU
VCO)
CPU
Off
Off
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