MPC8347VVALFB Freescale Semiconductor, MPC8347VVALFB Datasheet - Page 15
![IC MPU POWERQUICC II 672-TBGA](/photos/6/77/67707/mpc8347vvalfb_sml.jpg)
MPC8347VVALFB
Manufacturer Part Number
MPC8347VVALFB
Description
IC MPU POWERQUICC II 672-TBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC II PROr
Specifications of MPC8347VVALFB
Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
667MHz
Voltage
1.3V
Mounting Type
Surface Mount
Package / Case
672-TBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
MPC8349E-MITXE
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
Family Name
MPC83xx
Device Core
PowerQUICC II Pro
Device Core Size
32b
Frequency (max)
667MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.3V
Operating Supply Voltage (max)
1.36V
Operating Supply Voltage (min)
1.24V
Operating Temp Range
0C to 105C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
TBGA
Core Size
32 Bit
Program Memory Size
64KB
Cpu Speed
667MHz
Embedded Interface Type
I2C, SPI, USB, UART
Digital Ic Case Style
TBGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8347VVALFB
Manufacturer:
VIOCR
Quantity:
114
Company:
Part Number:
MPC8347VVALFB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8347VVALFB
Manufacturer:
FREESCALE
Quantity:
20 000
Table 11
6
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8347EA. Note that DDR SDRAM is GV
The AC electrical specifications are the same for DDR and DRR2 SDRAM.
6.1
Table 12
MPC8347EA when GV
Freescale Semiconductor
PLL lock times
DLL lock times
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
2. The csb_clk is determined by the CLKIN and system PLL ratio. See
I/O supply voltage
I/O reference voltage
I/O termination voltage
Input high voltage
Input low voltage
Output leakage current
Output high current (V
results in the minimum and an 8:1 ratio results in the maximum.
DDR and DDR2 SDRAM
lists the PLL and DLL lock times.
provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
DDR and DDR2 SDRAM DC Electrical Characteristics
Parameter/Condition
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
The information in this document is accurate for revision 3.0 silicon and
later. For information on revision 1.1 silicon and earlier versions see the
MPC8347E PowerQUICC II Pro Integrated Host Processor Hardware
Specifications. See
Document,” for silicon revision level determination.
Table 12. DDR2 SDRAM DC Electrical Characteristics for GV
Parameter/Condition
OUT
= 1.420 V)
DD
(typ) = 1.8 V
Section 22.1, “Part Numbers Fully Addressed by This
Table 11. PLL and DLL Lock Times
.
Symbol
MV
GV
V
I
V
I
V
OZ
OH
TT
REF
IH
IL
DD
DD
(typ) = 2.5 V and DDR2 SDRAM is GV
NOTE
MV
MV
0.49 × GV
REF
REF
–13.4
1.71
–0.3
–9.9
Min
7680
+ 0.125
Section 19, “Clocking.”
Min
– 0.04
—
DD
MV
122,880
MV
0.51 × GV
GV
Max
100
REF
REF
DD
Max
1.89
DD
9.9
—
– 0.125
+ 0.04
+ 0.3
(typ) = 1.8 V
DD
csb_clk cycles
DDR and DDR2 SDRAM
Unit
μs
DD
Unit
mA
μA
V
V
V
V
V
(typ) = 1.8 V.
Notes
Notes
1, 2
—
—
—
—
1
2
3
4
15