XS1-L01A-TQ128-C4-THS XMOS, XS1-L01A-TQ128-C4-THS Datasheet - Page 9

IC MPU 32BIT SINGLE CORE 128TQFP

XS1-L01A-TQ128-C4-THS

Manufacturer Part Number
XS1-L01A-TQ128-C4-THS
Description
IC MPU 32BIT SINGLE CORE 128TQFP
Manufacturer
XMOS
Datasheet

Specifications of XS1-L01A-TQ128-C4-THS

Processor Type
XCore 32-Bit
Speed
400MHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
128-TQFP Exposed Pad, 128-eTQFP, 128-HTQFP, 128-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
880-1023

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XS1-L01A-TQ128-C4-THS
Manufacturer:
XMOS
Quantity:
10 000
XS1-L1 128TQFP Datasheet (2.2)
XS1-L System
The MODE pins must be static for reliable operation.
When booting the XS1-L1 device from a SPI interface, the SPI device must be connected
Bits [1:0] control the PLL boot mode according to the following table:
If secure boot from OTP is enabled by programming the OTP, the boot mode indicated
on the MODE[3:2] pins is ignored. For further details on booting XCores see the
DEBUG This pin is used to synchronize the debugging of multiple XS1 devices.
RST_N Active low asynchronous-assertion global reset signal. At power-up, this pin
3.3 SPI Interface
to the XS1-L1 as follows:
MODE3
0
0
1
1
MODE1
0
0
1
1
This pin can operate in both output and input mode. In output mode and
when configured to do so, DEBUG is driven low by the device when the XCore
XCore into debug mode. Software can set the behavior of the XCore based
processor hits a debug break point. Prior to this point the pin will be tri-stated.
In input mode and when configured to do so, driving this pin low will put the
on this pin. If multi-device debug is not required then this pin can be left
unconnected.
must be activated for at least 5us after the power supplies are stable to ensure
reliable booting. Following a reset the PLL re-establishes lock after which the
device boots up according to the boot mode (see MODE).
MODE2
0
1
0
1
MODE0
0
1
0
1
Specification.
Boot Mode
None - Device will wait to be booted (via JTAG)
Reserved
XMOS Link B
SPI
PLL Multiplier Ratio
30.75
4
8.3333
20
PLL reference clk
4.22 to 13 MHz
21.66 to 100 MHz
10.4 to 48 MHz
4.33 to 20 MHz
Boot Frequency
130 to 399.75 MHz
86.66 to 400 MHz
86.66 to 400 MHz
86.66 to 400 MHz
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