MPC5200VR400 Freescale Semiconductor, MPC5200VR400 Datasheet - Page 37
![IC MPU 32BIT 400MHZ PPC 272-PBGA](/photos/6/78/67830/mpc5200vr400_sml.jpg)
MPC5200VR400
Manufacturer Part Number
MPC5200VR400
Description
IC MPU 32BIT 400MHZ PPC 272-PBGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC5200CVR400B.pdf
(80 pages)
Specifications of MPC5200VR400
Processor Type
MPC52xx PowerPC 32-Bit
Speed
400MHz
Voltage
1.5V
Mounting Type
Surface Mount
Package / Case
272-PBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC5200VR400
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MPC5200VR400
Manufacturer:
FRRESCAL
Quantity:
838
Company:
Part Number:
MPC5200VR400
Manufacturer:
MOTOLOLA
Quantity:
648
Company:
Part Number:
MPC5200VR400
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC5200VR400B
Manufacturer:
TI
Quantity:
233
Company:
Part Number:
MPC5200VR400B
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC5200VR400BR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale Semiconductor
NOTES:
1
2
(t)
(t)
t
is waiting for the other agent to respond with a signal before proceeding.
All timing parameters are measured at the connector of the drive to which the parameter applies. For example, the
sender shall stop generating STROBE edges t
measurements are taken at the connector of the sender. Even though the sender stops generating STROBE edges,
the receiver may receive additional STROBE edges due to propagation delays. All timing measurement switching
points (low to high and high to low) are taken at 1.5 V.
Name
(t)
(t)
(t)
(t)
(t)
(t)
UI
(t)
(t)
(t)
(t)
(t)
(t)
IORDYZ
ZIORDY
• t
• t
• t
, t
ZAH
ZAD
ENV
RFS
ACK
MLI
AZ
SR
RP
SS
UI
LI
MLI
UI
MLI
LI
is a limited time-out that has a defined maximum.
is an unlimited interlock that has no maximum time value.
, t
is a limited time-out that has a defined minimum.
LI
Min
160
indicate sender-to-recipient or recipient-to-sender interlocks. That is, one agent (either sender or recipient)
20
20
20
20
50
—
—
—
—
MODE 0
0
0
0
0
(ns)
Max
150
10
70
50
75
20
—
—
—
—
—
—
—
—
Table 29. Ultra DMA Timing Specification (continued)
Min
125
20
20
—
20
—
—
—
20
50
MODE 1
0
0
0
0
(ns)
Max
150
10
70
30
60
20
—
—
—
—
—
—
—
—
Min
100
20
20
20
20
50
—
—
—
—
MODE 2
0
0
0
0
MPC5200 Data Sheet, Rev. 4
(ns)
RFS
Max
150 Limited Interlock time.
—
—
10
—
—
70
20
50
—
20
—
—
—
after negation of DMARDY. Both STROBE and DMARDY timing
Interlock time with minimum.
Unlimited interlock time.
Maximum time allowed for output drivers to release
from being asserted or negated
Minimum delay time required for output drivers to
assert or negate from released state
Envelope time—from DMACK to STOP and
HDMARDY during data out burst initiation.
STROBE to DMARDY time, if DMARDY is negated
before this long after STROBE edge, the recipient
receives no more than one additional data word.
Ready-to-Final STROBE time—no STROBE edges
are sent this long after negation of DMARDY.
Ready-to-Pause time—the time recipient waits to
initiate pause after negating DMARDY.
Pull-up time before allowing IORDY to be released.
Minimum time drive waits before driving IORDY
Setup and hold times for DMACK, before assertion or
negation.
Time from STROBE edge to negation of DMARQ or
assertion of STOP, when sender terminates a burst.
Comment
1,2
1,2
Electrical and Thermal Characteristics
1,2
SpecID
A8.34
A8.35
A8.36
A8.37
A8.38
A8.39
A8.40
A8.41
A8.42
A8.43
A8.44
A8.45
A8.46
A8.47
37