MPC860PZQ80D4 Freescale Semiconductor, MPC860PZQ80D4 Datasheet - Page 5
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MPC860PZQ80D4
Manufacturer Part Number
MPC860PZQ80D4
Description
IC MPU POWERQUICC 80MHZ 357PBGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MC860DECVR50D4R2.pdf
(80 pages)
Specifications of MPC860PZQ80D4
Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
80MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Processor Series
MPC8xx
Core
MPC8xx
Data Bus Width
32 bit
Maximum Clock Frequency
80 MHz
Operating Supply Voltage
2.5 V, 3.3 V
Maximum Operating Temperature
+ 95 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC860PZQ80D4
Manufacturer:
MOTOLOLA
Quantity:
465
Company:
Part Number:
MPC860PZQ80D4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC860PZQ80D4
Manufacturer:
FREE
Quantity:
20 000
Company:
Part Number:
MPC860PZQ80D4R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale Semiconductor
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— Up to 8 Kbytes of dual-port RAM
— 16 serial DMA (SDMA) channels
— Three parallel I/O registers with open-drain capability
Four baud-rate generators (BRGs)
— Independent (can be tied to any SCC or SMC)
— Allows changes during operation
— Autobaud support option
Four serial communications controllers (SCCs)
— Ethernet/IEEE 802.3® standard optional on SCC1–4, supporting full 10-Mbps operation
— HDLC/SDLC (all channels supported at 2 Mbps)
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support point-to-point protocol (PPP)
— AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame-based with optional cyclic redundancy check (CRC))
Two SMCs (serial management channels)
— UART
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division multiplexed (TDM) channels
One SPI (serial peripheral interface)
— Supports master and slave modes
— Supports multimaster operation on the same bus
One I
— Supports master and slave modes
— Multiple-master environment support
Time-slot assigner (TSA)
— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame synchronization, and clocking
(available only on specially programmed devices)
2
C (inter-integrated circuit) port
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Features
5