MPC860DPZQ80D4 Freescale Semiconductor, MPC860DPZQ80D4 Datasheet - Page 4

• Manufacturer Part Number: MPC860DPZQ80D4
• Description: IC MPU POWERQUICC 80MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC860DPZQ80D4

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 80MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Features: -

Features
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System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Low-power stop mode
— Clock synthesizer
— Decrementer, time base, and real-time clock (RTC)
— Reset controller
— IEEE 1149.1™ Std. test access port (JTAG)
Interrupts
— Seven external interrupt request (IRQ) lines
— 12 port pins with interrupt capability
— 23 internal interrupt sources
— Programmable priority between SCCs
— Programmable highest priority request
10/100 Mbps Ethernet support, fully compliant with the IEEE 802.3u® Standard (not available
when using ATM over UTOPIA interface)
ATM support compliant with ATM forum UNI 4.0 specification
— Cell processing up to 50–70 Mbps at 50-MHz system clock
— Cell multiplexing/demultiplexing
— Support of AAL5 and AAL0 protocols on a per-VC basis. AAL0 support enables OAM and
— ATM pace control (APC) scheduler, providing direct support for constant bit rate (CBR) and
— Physical interface support for UTOPIA (10/100-Mbps is not supported with this interface) and
— UTOPIA-mode ATM supports level-1 master with cell-level handshake, multi-PHY (up to four
— Serial-mode ATM connection supports transmission convergence (TC) function for
Communications processor module (CPM)
— RISC communications processor (CP)
— Communication-specific commands (for example,
— Supports continuous mode transmission and reception on all serial channels
software implementation of other protocols.
unspecified bit rate (UBR) and providing control mechanisms enabling software support of
available bit rate (ABR)
byte-aligned serial (for example, T1/E1/ADSL)
physical layer devices), connection to 25-, 51-, or 155-Mbps framers, and UTOPIA/system
clock ratios of 1/2 or 1/3.
T1/E1/ADSL lines, cell delineation, cell payload scrambling/descrambling, automatic
idle/unassigned cell insertion/stripping, header error control (HEC) generation, checking, and
statistics.
MODE
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MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
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