MPC8360EZUAJDGA Freescale Semiconductor, MPC8360EZUAJDGA Datasheet - Page 86

• Manufacturer Part Number: MPC8360EZUAJDGA
• Description: IC MPU POWERQUICC II PRO 740TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8360EZUAJDGA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 740-TBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8360E-RDK
• Maximum Clock Frequency: 533 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• For Use With: MPC8360EA-MDS-PB - KIT APPLICATION DEV 8360 SYSTEMMPC8360E-RDK - BOARD REFERENCE DESIGN FOR MPC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clocking
Figure 55
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode. Note that in PCI host mode, the primary
clock input also depends on whether PCI clock outputs are selected with RCWH[PCICKDRV]. When the
device is configured as a PCI host device (RCWH[PCIHOST] = 1) and PCI clock output is selected
(RCWH[PCICKDRV] = 1), CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2)
and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration
input selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The
OCCR[PCIOENn] parameters enable the PCI_CLK_OUTn, respectively.
86
CFG_CLKIN_DIV
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
CLKIN
shows the internal distribution of clocks within the MPC8358E.
ce_clk to QUICC Engine Block
Engine
QUICC
MPC8358E
PLL
System
Figure 55. MPC8358E Clock Subsystem
PLL
e300 Core
PCI Clock
Clock
Divider
Unit
csb_clk
csb_clk to Rest
of the Device
ddr1_clk
lb_clk
Core PLL
LBIU
/n
DDRC
DLL
core_clk
/2
LCLK[0:2]
LSYNC_OUT
LSYNC_IN
MEMC1_MCK[0:5]
MEMC1_MCK[0:5]
PCI_CLK/
PCI_SYNC_IN
PCI_SYNC_OUT
PCI_CLK_OUT[0:2]
Freescale Semiconductor
Local Bus
Memory
Device
DDRC
Memory
Device