MC7447AHX1420LB Freescale Semiconductor, MC7447AHX1420LB Datasheet - Page 17

• Manufacturer Part Number: MC7447AHX1420LB
• Description: IC MPU RISC 1420MHZ 360-FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC7447AHX1420LB

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.42GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 360-FCCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Figure 4
Freescale Semiconductor
At recommended operating conditions. See
SYSCLK to ARTRY/SHD0/SHD1 high impedance after
precharge
Notes:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge
2. The symbology used for timing specifications herein follows the pattern of t
3. t
4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low and
5. Guaranteed by design and not tested.
6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately
7. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle
8. BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These
of the input SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to
the midpoint of the signal in question. All output timings assume a purely resistive 50-Ω load (see
and output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and
connectors in the system.
and t
state (V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And t
symbolizes the time from SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold
time can be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH)
(note the position of the reference and its state for inputs) and output hold time can be read as the time from the
rising edge (KH) until the output went invalid (OX).
the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
precharged high before returning to high impedance, as shown in
is 0.5 × t
the following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal
asserted. Output valid time is tested for precharge.The high-impedance behavior is guaranteed by design.
following AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any
master asserting it low in the first clock following AACK will then go to high impedance for 1 clock before
precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY
is 1.0 t
master to assert ARTRY. Output valid and output hold timing is tested for the signal asserted.The high-impedance
behavior is guaranteed by design.
of TS. Timing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated
for up to an entire cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge
width for SHD0 and SHD1 is 1.0 t
of core to bus (PLL configurations).
parameters represent the input setup and hold times for each sample. These values are guaranteed by design
and not tested. These inputs must remain stable after the second sample. See
sysclk
provides the AC test load for the MPC7447A.
(reference)(state)(signal)(state)
is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by
SYSCLK
SYSCLK
; that is, it should be high impedance as shown in
, that is, less than the minimum t
Table 9. Processor Bus AC Timing Specifications
Output
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
Parameter
Table
for outputs. For example, t
SYSCLK
4.
Z
. The edges of the precharge vary depending on the programmed ratio
Figure 4. AC Test Load
0
= 50 Ω
SYSCLK
period, to ensure that another master asserting TS on
IVKH
Symbol
t
KHARPZ
symbolizes the time input signals (I) reach the valid
Figure 6
Figure
2
R
L
All Speed Grades
= 50 Ω
Min
6. The nominal precharge width for TS
before the first opportunity for another
—
(signal)(state)(reference)(state)
1
Electrical and Thermal Characteristics
(continued)
Figure 5
OV
Max
2
DD
for sample timing.
/2
t
SYSCLK
Unit
Figure
KHOV
for inputs
3, 5, 6, 7
4). Input
Notes
17