Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 272
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number:
Z0847006PSG
Manufacturer:
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Table 7. Bisync Receive Mode
UM008101-0601
Function
Initialize WR0
< % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Register Information Loaded
WR0
WR2
WR0
WR4
WR0
WR5
WR0
WR3
WR0
WR6
WR0
WR7
CRC character has been loaded to the receive buffer, or 20 times (the
previous 16 plus 3-bit buffer delay and 1-bit input delay) after the last bit
is at the RxD input, before CRC calculation is complete. A faster external
clock can be gated to the Receive Clock input to supply the required 16
cycles. The Transmit and Receive Data Path diagram (Figure 109) illus-
trates the various points of delay in the CRC path.
The typical program steps that implement a half-duplex Bisync Receive
mode are illustrated in Table 7. The complete set of command and status
bit definitions are explained under
Typical Program Steps
Channel Reset, Reset Receive CRC
Checker
Pointer 2
Interrupt Vector
Pointer 4
Parity Information, Sync Modes
Information, Clock Mode
Pointer 5, Reset External Status
Interrupt
Bisync CRC-16, Data Terminal Ready
Pointer 3
Sync Character Load Inhibit, Receive
CRC Enable; Enter Hunt Mode, Auto
Enables, Receive Character Length
Pointer 6
Sync Character 1
Pointer 7
Sync Character 2
“Programming” on page
Comments
Reset SIO; initialize receive CRC
checker
Channel B only
Issue Receive Parameters
Sync Character Load Inhibit strips all
the leading sync characters at the
beginning of the message. Auto Enables
enables the receiver to accept data only
after the DCD input is active.
Serial Input/Output
272.
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