Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 38
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z0847006PSG
Manufacturer:
Zilog
Quantity:
22
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UM008101-0601
Bit
Number
4
3
2
1
0
*TIMER mode only
< % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Field
CLK/TRG Edge
Section
Time Trigger*
Time Constant
Reset
Control or Vector
Bit 7 = 1. Each channel is enabled to generate an interrupt request sequence
when the down-counter reaches a zero-count condition. To set the interrupt
bit to 1 in any of the four Channel Control registers an interrupt vector is
written to the CTC before operation begins. Channel interrupts may be
programmed in either Counter or Timer mode. If an updated channel
control word is written to a channel in operation, with bit 7 set, the interrupt
enable selection is not retroactive to a preceding zero-count condition.
Bit 7 = 0. Channel interrupts disabled.
Bit 6 = 1. Counter mode selected. The down-counter is decremented by
each triggering edge of the External clock (CLK/TRG) input. The prescaler
is not used.
Bit 6 = 0. Timer mode selected. The prescaler is clocked by the System
clock Φ, and the output of the prescaler in turn clocks the down-counter.
The output of the down-counter (the channel’s ZC/TO output) is a uniform
pulse train of period given by the product as shown below
8
-
R/W Value Description
R/W
R/W
R/W
R/W
R/W
$
0
1
0
1
0
1
0
1
0
1
Rising Edge
Falling Edge
CLK/TRG Pulse Starts Timer
Automatic trigger when time constant is loaded
Time Constant Follows
No Time Constant Follows
Software Reset
Continue Operation
Control
Vector
Counter/Timer Channels
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