EZ80L92AZ050EG Zilog, EZ80L92AZ050EG Datasheet - Page 170
EZ80L92AZ050EG
Manufacturer Part Number
EZ80L92AZ050EG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ050EG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3877
EZ80L92AZ050EG
EZ80L92AZ050EG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80L92AZ050EG
Manufacturer:
ZILOG
Quantity:
445
Company:
Part Number:
EZ80L92AZ050EG
Manufacturer:
ZiLOG
Quantity:
135
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PS013014-0107
ZDA
ZCL
ZDI Write Operations
ZDI Address
lsb of
A0
7
can be repeated. This allows repeated Read or Write operations without having to resend
the ZDI command. A START signal must follow to initiate a new ZDI command.
Figure 39
ZDI Single-Byte Write
For single-byte Write operations, the address and write control bit are first written to the
ZDI block. Following the single-bit byte separator, the data is shifted into the ZDI block
on the next 8 rising edges of ZCL. The master terminates activity after 8 clock cycles.
Figure 40
ZDA
ZCL
Write
8
Byte Separator
START
Signal
Single-Bit
illustrates the timing for address Writes to ZDI registers.
S
illustrates the timing for ZDI single-byte Write operations.
0/1
9
Figure 40. ZDI Single-Byte Data Write Timing
of DATA
msb
A6
msb
1
D7
1
Figure 39. ZDI Address Write Timing
A5
D6
2
2
A4
3
D5
3
ZDI Address Byte
A3
ZDI Data Byte
4
D4
4
A2
5
D3
5
A1
D2
6
6
A0
lsb
7
D1
Product Specification
7
0 = WRITE
1 = READ
ZiLOG Debug Interface
R/W
of DATA
8
Byte Separator
START Signal
D0
lsb
8
or new ZDI
eZ80L92 MCU
Single-Bit
START Signal
End of Data
or New ZDI
0/1
9
1
9
164
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