MPC8347EVVAJDB Freescale Semiconductor, MPC8347EVVAJDB Datasheet - Page 27

• Manufacturer Part Number: MPC8347EVVAJDB
• Description: IC MPU PWRQUICC II 672-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8347EVVAJDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 672-TBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 672
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Figure 12
8.2.3
This section describes the TBI transmit and receive AC timing specifications.
8.2.3.1
Table 25
Freescale Semiconductor
At recommended operating conditions with LV
GTX_CLK clock period
GTX_CLK duty cycle
GTX_CLK to TBI data TXD[7:0], TX_ER, TX_EN delay
GTX_CLK clock rise, V
GTX_CLK clock fall time, V
GTX_CLK125 reference clock period
GTX_CLK125 reference clock duty cycle
Notes:
1. The symbols for timing specifications follow the pattern of t
2. This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention
and t
timing (TT) with respect to the time from t
or setup time. Also, t
the referenced data signals (D) reach the invalid state (X) or hold time. In general, the clock reference symbol is based on
three letters representing the clock of a particular function. For example, the subscript of t
(TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
(first two letters of functional block)(reference)(state)(signal)(state)
provides the TBI transmit AC timing specifications.
shows the MII receive AC timing diagram.
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11
TBI AC Timing Specifications
TBI Transmit AC Timing Specifications
RXD[3:0]
Parameter/Condition
RX_CLK
RX_DV
RX_ER
TTKHDX
IL
(min) to V
IH
(max) to V
symbolizes the TBI transmit timing (TT) with respect to the time from t
Table 25. TBI Transmit AC Timing Specifications
IH
(max)
Figure 12. MII Receive AC Timing Diagram
t
t
MRXH
IL
MRDVKH
DD
(min)
/OV
TTX
t
DD
MRX
(K) going high (H) until the referenced data signals (D) reach the valid state (V)
of 3.3 V ± 10%.
Valid Data
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
t
G125H
t
t
Symbol
TTXH
MRXF
t
TTKHDX
t
t
t
G125
t
TTXR
TTXF
TTX
/t
/t
TTX
G125
2
1
t
MRDXKH
t
MRXR
Ethernet: Three-Speed Ethernet, MII Management
Min
1.0
40
45
—
—
—
—
TTKHDV
TTX
Typ
represents the TBI (T) transmit
8.0
8.0
symbolizes the TBI transmit
—
—
—
—
—
TTX
(K) going high (H) until
Max
5.0
1.0
1.0
60
55
—
—
for inputs
Unit
ns
ns
ns
ns
ns
ns
%
27