MPC8347EVVAJDB Freescale Semiconductor, MPC8347EVVAJDB Datasheet - Page 43

• Manufacturer Part Number: MPC8347EVVAJDB
• Description: IC MPU PWRQUICC II 672-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8347EVVAJDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 672-TBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 672
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Figure 26
Figure 27
Freescale Semiconductor
At recommended operating conditions (see
Output hold times:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
2. The symbols for timing specifications follow the pattern of t
4. Non-JTAG signal input timing with respect to t
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design and characterization.
JTAG external clock to output high impedance:
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
and t
(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
The output timings are measured at the pins. All output timings assume a purely resistive 50 Ω load (see
to the high (H) state or setup time. Also, t
went invalid (X) relative to the t
based on three letters representing the clock of a particular function. For rise and fall times, the latter convention is used with
the appropriate letter: R (rise) or F (fall).
(first two letters of functional block)(reference)(state)(signal)(state)
provides the AC test load for TDO and the boundary-scan outputs of the MPC8347E.
provides the JTAG clock input timing diagram.
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11
External Clock
Table 37. JTAG AC Timing Specifications (Independent of CLKIN)
Parameter
JTAG
Output
JTG
Figure 26. AC Test Load for the JTAG Interface
Figure 27. JTAG Clock Input Timing Diagram
Boundary-scan data
Boundary-scan data
clock reference (K) going to the high (H) state. In general, the clock reference symbol is
Table
VM
t
JTKHKL
JTDXKH
2).
VM = Midpoint Voltage (OV DD /2)
TCLK
Z
t
JTG
TCLK
0
symbolizes JTAG timing (JT) with respect to the time data input signals (D)
= 50 Ω
TDO
TDO
.
VM
.
for outputs. For example, t
(first two letters of functional block)(signal)(state)(reference)(state)
Symbol
t
t
t
t
JTKLDX
JTKLOX
JTKLOZ
JTKLDZ
VM
2
R
L
= 50 Ω
Min
TCLK
t
2
2
2
2
JTGR
to the midpoint of the signal in question.
JTDVKH
OV
DD
1
Max
symbolizes JTAG device timing
19
—
—
t
9
(continued)
JTG
JTGF
/2
clock reference (K) going
Unit
ns
ns
Figure
for inputs
26).
Notes
5, 6
5
JTAG
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