MC68EC030CFE25C Freescale Semiconductor, MC68EC030CFE25C Datasheet

Page 1

... Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Technical Summary Second-Generation 32-Bit Enhanced Embedded Controller The MC68EC030 is a 32-bit embedded controller that streamlines the functionality of an MC68030 for the requirements of embedded control applications. The MC68EC030 is optimized to maintain performance while using cost-effective memory subsystems. The rich instruction set and addressing mode capabilities of the MC68020, MC68030, and MC68040 have been maintained, allowing a clear migration path for M68000 systems ...

Page 2

... Freescale Semiconductor, Inc. The MC68EC030 is an integrated controller that incorporates the capabilities of the MC68030 integer unit, a data cache, an instruction cache, an access control unit (ACU), and an improved bus controller on one VLSI device. It maintains the 32-bit registers available with the entire M68000 Family as well as the 32-bit address and data paths, rich instruction set, versatile addressing modes, and flexible coprocessor interface provided with the MC68020 and MC68030 ...

Page 3

... Freescale Semiconductor, Inc. information. The instruction pipe and other individual control sections provide the secondary decode of instructions and generate the actual control signals that result in the decoding and interpretation of nanoROM and microROM information. The instruction and data cache blocks operate independently from the rest of the machine, storing information read by the bus controller for future use with very fast access time ...

Page 4

... Freescale Semiconductor, Inc. 4 MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com ...

Page 5

... Freescale Semiconductor, Inc. The ACU contains two access control registers that are used to define memory segments ranging in size from 16 Mbytes to 2 Gbytes each. Each segment is definable in terms of address, read/write access, and function code. Each segment can be marked as cacheable or non cacheable to control cache accesses to that memory space ...

Page 6

... Freescale Semiconductor, Inc Figure 4. Supervisor Programming Model Supplement The status register (see Figure 5) contains the interrupt priority mask (three bits) as well as the following condition codes: extend (X), negate (N), zero (Z), overflow (V), and carry (C). Additional control bits indicate that the controller is in the trace mode (T1 or T0), supervisor/user state (S), and master/interrupt state (M) ...

Page 7

... Freescale Semiconductor, Inc. All microprocessors of the M68000 Family support instruction tracing (via the T0 status bit in the MC68EC030) where each instruction executed is followed by a trap to a user-defined trace routine. The MC68EC030, like the MC68030 and MC68040, also has the capability to trace only on change-of-flow instructions (branch, jump, subroutine call and return, etc ...

Page 8

... Freescale Semiconductor, Inc. In addition, operations on other data types, such as memory addresses, status word data, etc., are provided in the instruction set. The coprocessor mechanism allows direct support of floating-point data types with the MC68881/MC68882 floating-point coprocessors as well as specialized user-defined data types and functions. The 18 addressing modes, listed in Table 1, include nine basic types: • ...

Page 9

... Freescale Semiconductor, Inc. Table 1. MC68EC030 Addressing Modes Addressing Modes Register Direct Addressing Data Register Direct Address Register Direct Register Indirect Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement Address Register Indirect with Displacement Register Indirect with Index ...

Page 10

... Freescale Semiconductor, Inc. INSTRUCTION SET OVERVIEW The MC68EC030 instruction set is listed in Table 2. Each instruction, with few exceptions, operates on bytes, words, and long words, and most instructions can use any of the 18 addressing modes. The MC68EC030 is upward source- and object-level code compatible with the M68000 Family because it supports all instructions of previous family members ...

Page 11

... Freescale Semiconductor, Inc. cpBCC Branch Conditionally cpDBcc Test Coprocessor Condition, Decrement and Branch cpGEN Coprocessor General Instruction Included in the MC68EC030 set are the bit field operations, binary-coded decimal support, bounds checking, additional trap conditions, and additional multiprocessing support (CAS and CAS2 instructions) offered by the MC68020, MC68030, and MC68040 ...

Page 12

... Freescale Semiconductor, Inc. The MC68EC030 instruction cache is a 256-byte direct-mapped cache organized as 16 lines consisting of four long words per line. Each long word is independently accessible, yielding 64 possible entries, with address bit A1 selecting the correct word during an access. Thus, each line has a tag field composed of the upper 24 address bits, the FC2 (supervisor/user) value, four valid bits (one for each long-word entry), and the four long-word entries (see Figure 6) ...

Page 13

... Freescale Semiconductor, Inc. DATA CACHE The organization of the data cache (see Figure 7) is similar to that of the instruction cache. However, the tag is composed of the upper 24 address bits, the four valid bits, and all three function code bits, explicitly specifying the address space associated with each line. The data cache employs a write-through policy with programmable write allocation of data writes— ...

Page 14

... Freescale Semiconductor, Inc. thereby increasing possible performance. Burst mode transfers can be used to fill lines of the instruction and data caches when the MC68EC030 asserts cache burst request ( STERM cycle with , subsequent cycles may accept data on every clock cycle where until the burst is completed. Use of this mode can further increase the available bus bandwidth in systems that use DRAMs with page, nibble, or static-column mode operation ...

Page 15

... Freescale Semiconductor, Inc. SYNCHRONOUS TRANSFERS Synchronous bus cycles are terminated by asserting transfer is for 32 bits. Since this input is not synchronized internally, two-clock-cycle bus accesses can be performed if the signal is valid one clock after the beginning of the bus cycle with the appropriate setup time. However, the bus cycle may be lengthened by delaying increments) until the device being accessed is able to terminate the cycle ...

Page 16

... Freescale Semiconductor, Inc. EXCEPTION PROCESSING SEQUENCE Exception processing occurs in four steps. During the first step, an internal copy is made of the status register. After the copy is made, the special controller state bits in the status register are changed. The S- bit is set, putting the controller into the supervisor state. Also, the T1 and T0 bits are negated, allowing the exception handler to execute unhindered by tracing ...

Page 17

... Freescale Semiconductor, Inc. ACCESS CONTROL Two access control registers are provided on the MC68EC030 to control cachability of accesses for two independent blocks of memory. Each block can range in size from 16 Mbytes to 2 Gbytes, and is specified in the corresponding ACx register with a base address, a base mask, function code, function code mask, and read/write mask ...

Page 18

... Freescale Semiconductor, Inc. Signal Name Mnemonic Function Codes Address Bus Data Bus Size Operand Cycle Start External Cycle Start Read/Write Read-Modify-Write Cycle Address Strobe Data Strobe Data Buffer Enable Data Transfer and Size Acknowledge Synchronous Termination Cache Inhibit In Cache Inhibit Out ...

Page 19

... Freescale Semiconductor, Inc. Clock Signal Name Mnemonic Power Supply Ground No Connect CLK Clock input to the controller. Table 3. Signal Index – Continued V CC Power supply. GND Ground connection not connect. MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com Function 1 9 ...

Page 20

... Freescale Semiconductor, Inc. ELECTRICAL SPECIFICATIONS MAXIMUM RATINGS Rating Supply Voltage Input Voltage Operating Temperature Range Minimum Ambient Temperature Maximum Ambient Temperature Storage Temperature Range THERMAL CHARACTERISTICS-- PGA PACKAGE Characteristic Symbol Rating Thermal Resistance - Plastic Junction to Ambient Junction to case POWER CONSIDERATIONS The average chip-junction temperature, TJ, in ...

Page 21

... Freescale Semiconductor, Inc. The total thermal resistance of a package ( JA ) can be separated into two components, representing the barrier to heat flow from the semiconductor junction to the package (case) surface ( JC ) and from the case to the outside ambient air ( CA ). These terms are related by the equation device related and cannot be influenced by the user ...

Page 22

... Freescale Semiconductor, Inc. CLK DRIVE TO 0.5 V 2.0 V VALID OUTPUTS(1) CLK OUTPUT n 0.8 V OUTPUTS(2) CLK DRIVE TO 2.4 V INPUTS(3) CLK DRIVE TO 0.5 V INPUTS(4) CLK ALL SIGNALS(5) NOTES: 1. This output timing is applicable to all parameters specified relative to the rising edge of the clock. 2. This output timing is applicable to all parameters specified relative to the falling edge of the clock. ...

Page 23

... Freescale Semiconductor, Inc. DC ELECTRICAL SPECIFICATIONS (V CC =5.0 Vdc ; GND=0Vdc; temperature in defined ranges) Characteristics Input High Voltage Input Low Voltage Input Leakage Current GND Hi-Z (Off-State) Leakage A0-A31, Current @ 2.4 V/0.5 V Output High Voltage 400 A Output Low Voltage 3.2 mA A0–A31, FC0–FC2, SIZ0–SIZ1 ...

Page 24

... Freescale Semiconductor, Inc. 2 Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V, unless otherwise noted. NOTE: The voltage swing through this range should start outside and pass through the range so that the rise or fall will be linear between 0 ...

Page 25

... Freescale Semiconductor, Inc. AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES (Continued Characterstics 8 15A DS Negated to AS Asserted 16 Clock High Negated Clock High to R/ High W 20 Clock High to R/ Low High to AS Asserted Low to DS Asserted (Write) 23 Clock High to Data-Out Valid 24 Data-Out Valid to Negating Edge of ...

Page 26

... Freescale Semiconductor, Inc. AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES (Concluded Characterstics Low to DBEN Asserted (Write) DBEN Width Asserted 5 45 DBEN Width Asserted 9 45A Width Asserted (Asynchronous Write or Read) 46A R/ W Width Asserted (Synchronous Write or Read) 47A Asynchronous Input Setup Time to Clock Low ...

Page 27

... Freescale Semiconductor, Inc This number can be reduced strobes have equal loads the asynchronous setup time (#47A) requirements are satisfied, the (#31) and DSACKx low to data-in clock low setup time (#27) for the following clock cycle and BERR low to clock low setup time (#27A) for the following clock cycle. ...

Page 28

... Freescale Semiconductor, Inc. FC2-FC0 SIZ1-SIZ0 ASYNCHRONOUS Figure 11 CLK 6 A31-A0 6A RMC 12A 10A ECS 10 6A OCS R DBEN 40 45 DSACK0 31A DSACK1 31 D31-D0 27 BERR HALT 47A ALL INPUTS 60 CIIN 61 CBREQ Asynchronous Read Cycle Timing Diagram MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www ...

Page 29

... Freescale Semiconductor, Inc. CLK A31-A0, FC2-FC0 SIZ1-SIZ0 RMC ECS OCS AS DS R/W DBEN DSACK0 DSACK1 D31-D0 BERR HALT CIOUT Figure 12 12A 10 10B 10A 14A 31A 27A Asynchronous Write Cycle Timing Diagram MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com ...

Page 30

... Freescale Semiconductor, Inc. A31-A0, FC2-FC0 SIZ1-SIZ0 DSACK0/DSACK1 Figure 13 CLK RMC 6 12A ECS 6A OCS 14B 46A R/W 40 DBEN CIOUT CBREQ 61 STERM 60 CIIN CBACK D31-D0 27 Synchronous Read Cycle Timing Diagram MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com 45A 12 30A ...

Page 31

... Freescale Semiconductor, Inc. A31-A0, FC2-FC0 SIZ1-SIZ0 D31-D0 DSACK0/DSACK1 STERM CBREQ Figure 14 CLK 6 RMC 12A ECS 6A OCS 9 AS 14B DS 20 46A R/W 42 45A DBEN BERR HALT 27A Synchronous Write Cycle Timing Diagram MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com ...

Page 32

... Freescale Semiconductor, Inc. S0 CLK A31-A0 D31-D0 FC2-FC0 SIZ1-SIZ0 ECS OCS AS DS R/W DBEN DSACK0 DSACK1 BR BG BGACK Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V, unless otherwise noted. NOTE: The voltage swing through this range should start outside and pass through the range so that the rise or fall will be linear between 0 ...

Page 33

... Freescale Semiconductor, Inc. CLK IPEND CDIS STATUS REFILL 47A 62 Figure 16. Other Signal Timings MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com ...

Page 34

... Freescale Semiconductor, Inc. PIN ASSIGNMENTS — PIN GRID ARRAY (RC SUFFIX DBEN ECS L CIIN SIZ0 K CBREQ J CBACK H BERR G STERM F DSACK0 FC1 B A The MC68030 has four additional guide pins not present on the MC68EC030. Therefore, an MC68EC030 fits in a socket designed for the MC68030, but the MC68030 does not necessary fit in a socket intended for the MC68EC030 ...

Page 35

... Freescale Semiconductor, Inc. PACKAGE DIMENSIONS MC68EC030 RP SUFFIX PACKAGE CASE 789F-01 B MILLIMETERS INCHES DIM MIN MAX MIN A 34.04 35.05 1.340 34.04 35.05 1.340 B C 3.18 2.92 0.115 D 0.44 0.55 0.017 G 2.54 BSC 0.100 BSC 4.32 4.95 K 0.170 L 1.02 1.52 0.040 2.79 M 3.81 ...

Page 36

... Freescale Semiconductor, Inc. Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not ...