MC68EC030CFE25C Freescale Semiconductor, MC68EC030CFE25C Datasheet - Page 15

• Manufacturer Part Number: MC68EC030CFE25C
• Description: IC MPU 32BIT ENH 25MHZ 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC030CFE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

SYNCHRONOUS TRANSFERS
BURST READ CYCLES
TYPES OF EXCEPTIONS
M O T O R O L A
Synchronous bus cycles are terminated by asserting
transfer is for 32 bits. Since this input is not synchronized internally, two-clock-cycle bus accesses can be
performed if the signal is valid one clock after the beginning of the bus cycle with the appropriate setup
time. However, the bus cycle may be lengthened by delaying
increments) until the device being accessed is able to terminate the cycle. After the assertion of
these cycles may be aborted upon the assertion of
assertion of
The MC68EC030 provides support for burst filling of its on-chip instruction and data caches, adding to
the overall system performance. The on-chip caches are organized with a line size of four long words;
there is only one tag for the four long words in a line. Since locality of reference is present to some
degree in most programs, filling of all four entries when a single entry misses can be advantageous,
especially if the time spent filling the additional entries is minimal. When the caches are burst filled, data
can be latched by the controller in as little as one clock for each 32 bits. Burst read cycles can be
performed only when the MC68EC030 requests them (with the assertion of
first cycle is a synchronous cycle as previously described. If the cache burst acknowledge (
is valid at the appropriate time in the synchronous bus cycle, the controller keeps the original
R/
of each subsequent clock cycle that has
complete (the entire block has been transferred),
inhibit in (
bursting enables the MC68EC030 to take advantage of cost-effective DRAM technology with minimal
performance impact.
The types of exceptions and the exception processing sequence are discussed in the following
paragraphs.
Exceptions can be generated by either internal or external causes. The externally generated exceptions
are interrupts,
whereas,
exceptions come from instructions, address errors, tracing, or breakpoints. The TRAP, TRAPcc,
TRAPVcc, cpTRAPcc, CKH, CKH2, and DIV instructions can all generate exceptions as part of instruction
execution. Tracing behaves like a very high-priority, internally generated interrupt whenever it is
processed. The other internally generated exceptions are caused by illegal instructions, instruction
fetches from odd addresses, and privilege violations.
W
, address, function code, and size outputs asserted and latches 32 bits from the data bus at the end
CIIN)
BERR
BERR
BERR
input is asserted, or the
and
and
RESET
, and
HALT
RESET
Freescale Semiconductor, Inc.
are used for access control and controller restart. The internally generated
.
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MC68EC030 TECHNICAL DATA
. Interrupts are requests from peripheral devices for controller action;
EXCEPTIONS
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CBACK
STERM
input is negated. The cache preloading allowed by the
BERR
asserted. This procedure continues until the burst is
BERR
STERM
is asserted in lieu of or after
, or they may be retried with the simultaneous
, which automatically indicates that the bus
STERM
(inserting wait states in one-clock
CBREQ
) and only when the
STERM
C BAC K)
, the cache
STERM,
AS
,
input
DS
,
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