XPC8240LZU200E Freescale Semiconductor, XPC8240LZU200E Datasheet - Page 5

MCU HOST PROCESSOR 352-TBGA

XPC8240LZU200E

Manufacturer Part Number
XPC8240LZU200E
Description
MCU HOST PROCESSOR 352-TBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC IIr
Datasheets

Specifications of XPC8240LZU200E

Processor Type
MPC82xx PowerQUICC II 32-bit
Speed
200MHz
Voltage
2.5V
Mounting Type
Surface Mount
Package / Case
352-TBGA
Core Size
32 Bit
Program Memory Size
32KB
Cpu Speed
200MHz
Embedded Interface Type
I2C
Digital Ic Case Style
TBGA
No. Of Pins
352
Supply Voltage Range
2.5V To 2.75V
Rohs Compliant
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-

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Notes:
1. The processor HID1 values only represent the multiplier of the processor’s PLL (memory-to-processor multiplier);
2. PLL_CFG[0:4] settings not listed (00110, 01001, 01011, 01101, 01111, 10001, 10011, 10101, 10111, 11001, and
3. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL
4. In clock-off mode, no clocking occurs inside the MPC8240 regardless of the PCI_SYNC_IN input.
5. Limited due to maximum memory VCO = 225 MHz.
6. Limited due to minimum CPU VCO = 200 MHz.
7. Limited due to minimum memory VCO = 100 MHz.
8. For clarity, range values are shown rounded down to the nearest whole number (decimal place accuracy removed).
9. Note that the 250-MHz part is available only in the XPC8240RZUnnnx number series.
1.9
Ordering information for the parts fully covered by this specification document is provided in Section 1.9.1,
“Part Numbers Fully Addressed by This Document.”
MPC8240 Part Number Specification for the XPC8240RXXnnnx Series
Ref.
No.
1A
1C
1D
1E
10
12
14
16
18
1F
thus, multiple MPC8240 PLL_CFG[0:4] values may have the same processor HID1 value. This implies that system
software cannot read the HID1 register and associate it with a unique PLL_CFG[0:4] value.
11011) are reserved.
is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware modeling
support. The AC timing specifications given in this document do not apply in PLL bypass mode.
A
C
E
5
7
8
[0:4]
00101
01000
01010
10000
10010
10100
00111
01100
01110
10110
11000
11010
11100
11101
11110
11111
PLL_
CFG
Ordering Information
2
Table 18. MPC8240 Microprocessor PLL Configurations (continued)
HID1[0:4]
CPU
00100
00100
00110
11000
11000
00111
00110
11000
11010
11000
11010
11000
00110
11110
01111
11111
1
Freescale Semiconductor, Inc.
PCI Clock Input
(PCI_SYNC_IN)
Range (MHz)
For More Information On This Product,
33
50
33
33
25–27
25–50
25–41
25–33
33–66
25–35
25–31
25–33
6
7
7
7
–56
–62
–55
–66
5
Go to: www.freescale.com
250-MHz Part
Bus Clock Range
Not usable
Logic/Mem
Peripheral
Bypass
Bypass
50–100
75–100
50–100
50–100
(MHz)
33–56
50–55
50–83
50–71
50–62
62–83
50–62
50–83
8, 9
CPU Clock
100–168
225–250
125–250
150–250
150–200
100–200
175–250
200–250
186–250
200–250
150–250
125–250
Range
(MHz)
PCI to Mem
(Mem VCO)
Multiplier
Bypass
Bypass
1.5 (3)
2.5 (5)
1.5 (3)
1.5 (3)
2 (4)
1 (4)
2 (4)
2 (4)
3 (6)
2 (4)
2 (4)
1 (2)
Off
Off
Ordering Information
Ratios
Mem to CPU
3, 4
(CPU VCO)
Multiplier
2.5 (5)
4.5 (9)
2.5 (5)
3.5 (7)
2.5 (5)
3 (6)
3 (6)
3 (6)
2 (4)
2 (4)
4 (8)
3 (6)
4 (8)
3 (6)
Off
Off
5

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