MC68HC000RC12 Freescale Semiconductor, MC68HC000RC12 Datasheet - Page 57

• Manufacturer Part Number: MC68HC000RC12
• Description: IC MPU 32BIT 12MHZ 68-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000RC12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 12MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 68
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The breakpoint acknowledge cycle is performed by the MC68010 to provide an indication
to hardware that a software breakpoint is being executed when the processor executes a
breakpoint (BKPT) instruction. The processor neither accepts nor sends data during this
cycle, which is otherwise similar to a read cycle. The cycle is terminated by either DTACK,
BERR, or as an M6800 peripheral cycle when V P A is asserted, and the processor
continues illegal instruction exception processing. Figure 5-12 illustrates the timing
diagram for the breakpoint acknowledge cycle.
5.2 BUS ARBITRATION
Bus arbitration is a technique used by bus master devices to request, to be granted, and
to acknowledge bus mastership. Bus arbitration consists of the following:
There are two ways to arbitrate the bus, 3-wire and 2-wire bus arbitration. The MC68000,
MC68HC000, MC68EC000, MC68HC001, MC68008, and MC68010 can do 2-wire bus
arbitration. The MC68000, MC68HC000, MC68HC001, and MC68010 can do 3-wire bus
arbitration. Figures 5-13 and 5-15 show 3-wire bus arbitration and Figures 5-14 and 5-16
show 2-wire bus arbitration. Bus arbitration on all microprocessors, except the 48-pin
MC68008 and MC68EC000, BGACK must be pulled high for 2-wire bus arbitration.
MOTOROLA
1. Asserting a bus mastership request
2. Receiving a grant indicating that the bus is available at the end of the current cycle
3. Acknowledging that mastership has been assumed
FC2–FC0
A23–A1
D15–D8
DTACK
D7–D0
UDS
LDS
CLK
R/W
AS
Figure 5-12. Breakpoint Acknowledge Cycle Timing Diagram
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M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
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WORD READ
Freescale Semiconductor, Inc.
For More Information On This Product,
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Go to: www.freescale.com
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BREAKPOINT
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CYCLE
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STACK PC LOW
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5- 11