MC68HC000RC12 Freescale Semiconductor, MC68HC000RC12 Datasheet - Page 77

• Manufacturer Part Number: MC68HC000RC12
• Description: IC MPU 32BIT 12MHZ 68-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000RC12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 12MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 68
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

LEGEND:
NOTE: All operations are subject to relevant setup and hold times.
The negation of BERR and HALT under several conditions is shown in Table 5-6. (DTACK
is assumed to be negated normally in all cases; for reliable operation, both DTACK and
BERR should be negated when address strobe is negated).
EXAMPLE A:
EXAMPLE B:
MOTOROLA
NA — Signal not asserted in this bus state
Case
No.
N — The number of the current even bus state (e.g., S4, S6, etc.)
A — Signal asserted in this bus state
X — Don't care
S — Signal asserted in preceding bus state and remains asserted in this state
A system uses a watchdog timer to terminate accesses to unused address space. The
timer asserts BERR after timeout (case 3).
A system uses error detection on random-access memory (RAM) contents. The system
designer may:
1
2
3
4
5
6
1. Delay DTACK until the data is verified. If data is invalid, return BERR and HALT
2. Delay DTACK until the data is verified. If data is invalid, return BERR at the same
3. For an MC68010, return DTACK before data verification. If data is invalid, assert
simultaneously to retry the error cycle (case 5).
time as DTACK (case 3).
BERR and HALT to retry the error cycle (case 6).
Control
DTACK
DTACK
DTACK
DTACK
DTACK
DTACK
Signal
BERR
BERR
BERR
BERR
BERR
BERR
HALT
HALT
HALT
HALT
HALT
HALT
Table 5-1.
Asserted on
Rising Edge
A/S
A/S
NA
NA
NA
NA
NA
NA
NA
NA
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
N
A
A
X
A
A
X
A
A
of State
N+2
Freescale Semiconductor, Inc.
NA
NA
NA
NA
S
X
S
S
X
S
S
A
X
S
S
S
A
A
For More Information On This Product,
DTACK
Normal cycle terminate and continue.
Normal cycle terminate and halt.
Continue when HALT negated.
Terminate and take bus error trap.
Normal cycle terminate and continue.
Terminate and retry when HALT
removed.
Normal cycle terminate and continue.
MC68000/MC68HC000/001
Go to: www.freescale.com
EC000/MC68008 Results
,
BERR
, and
HALT
Assertion Results
Normal cycle terminate and continue.
Normal cycle terminate and halt.
Continue when HALT negated.
Terminate and take bus error trap.
Terminate and take bus error trap.
Terminate and retry when HALT
removed.
Terminate and retry when HALT
removed.
MC68010 Results
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