MC68360CVR25L Freescale Semiconductor, MC68360CVR25L Datasheet - Page 281
MC68360CVR25L
Manufacturer Part Number
MC68360CVR25L
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360CVR25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
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Manufacturer:
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Quantity:
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DBFE—Double Bus Fault Monitor Enable
BME—Bus Monitor External Enable
BMT1–BMT0—Bus Monitor Timing
6.9.3.6 PERIODIC INTERRUPT CONTROL REGISTER (PICR). The PICR contains the
interrupt level and the vector number for the periodic interrupt request. This register can be
read or written at any time. Bits 15–11 are unimplemented and always return zero; a write
to these bits has no effect.
PIRQL2–PIRQL0—Periodic Interrupt Request Level
RESET:
These bits select the timeout period for the bus monitor (see Table 6-5).
15
These bits contain the periodic interrupt request level. Table 6-6 lists which interrupt re-
quest level is asserted during an interrupt acknowledge cycle when a periodic interrupt is
generated. The PIT continues to run when the interrupt is disabled.
0
0
1 = Enable the double bus fault monitor function. (Default)
0 = Disable the double bus fault monitor function.
For more information, see 6.3.1.2.3 Double Bus Fault Monitor and Section 5 CPU32+.
0 = Enable bus monitor function for the external bus cycles.
1 = Disable bus monitor function for the external bus cycles. (Default)
For more information see 6.3.1.2.1 Bus Monitor.
14
0
0
When the SWP and SWT bits are modified to select a software
timeout other than the default, the software service sequence
($55 followed by $AA written to the software service register)
must be performed before the new timeout period takes effect.
Use caution with a level 7 interrupt encoding due to the SIM60
interrupt servicing order. See 6.3.1.2 Simultaneous SIM60 Inter-
rupt Sources for the servicing order.
13
0
0
12
0
0
BMT1
Freescale Semiconductor, Inc.
11
0
0
1
1
0
0
For More Information On This Product,
PIRQL2 PIRQL1 PIRQL0
10
0
Table 6-5. BMT Encoding
BMT0
MC68360 USER’S MANUAL
Go to: www.freescale.com
0
1
0
1
9
0
1K System Clocks (CLKO1 Clocks)
512 System Clocks
256 System Clocks
128 System Clocks
NOTE
NOTE
8
0
Bus Monitor Timeout Period
PIV7
7
0
PIV6
6
0
PIV5
System Integration Module (SIM60)
5
0
PIV4
4
0
PIV3
3
1
PIV2
2
1
SUPERVISOR ONLY
PIV1
1
1
PIV0
0
1
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