MPC8245ARZU400D Freescale Semiconductor, MPC8245ARZU400D Datasheet - Page 5

IC MPU 32BIT 400MHZ 352-TBGA

MPC8245ARZU400D

Manufacturer Part Number
MPC8245ARZU400D
Description
IC MPU 32BIT 400MHZ 352-TBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8245ARZU400D

Processor Type
MPC82xx PowerQUICC II 32-bit
Speed
400MHz
Voltage
2.1V
Mounting Type
Surface Mount
Package / Case
352-TBGA
Processor Series
MPC8xxx
Core
603e
Data Bus Width
32 bit
Maximum Clock Frequency
400 MHz
Operating Supply Voltage
2 V, 2.1 V, 3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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2
Register settings that define each DLL mode are shown in
The DLL_MAX_DELAY bit can lengthen the amount of time through the delay line. This is accomplished
by increasing the time between each of the 128 tap points in the delay line. Although this increased time
makes it easier to guarantee that the reference clock will be within the DLL lock range, it also means there
may be slightly more jitter in the output clock of the DLL, should the phase comparator shift the clock
between adjacent tap points. Refer to Freescale application note AN2164, MPC8245/MPC8241 Memory
Clock Design Guidelines:Part 1, for details about DLL modes and memory design.
The value of the current tap point once the DLL has locked can be determined by reading bits 6–0
(DLL_TAP_COUNT) of the DLL tap count register (DTCR, located at offset 0xE3). These bits store the
value (binary 0 through 127) of the current tap point and can indicate whether the DLL advances or
decrements as it maintains the DLL lock. Therefore, for evaluation purposes, DTCR can be read for all
DLL modes that support the T
SDRAM_SYNC_IN. The DLL mode that provides the smallest tap point value seen in DTCR should be
used. This is because the bigger the tap point value, the more jitter that can be expected for clock signals.
Note that keeping a DLL mode that is locked below tap point 12 is not recommended.
Freescale Semiconductor
MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
Normal tap delay,
No DLL extend
Normal tap delay,
DLL extend
Max tap delay,
No DLL extend
Max tap delay,
DLL extend
DLL Mode
loop
value that is used for the trace length of SDRAM_SYNC_OUT to
Table 9. DLL Mode Definition
Value of Bit 2 of Config
Register at 0x76
0
0
1
1
Table
9.
Value of Bit 7 of Config
Register at 0x72
Electrical and Thermal Characteristics
0
1
0
1
5

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