MC68030RC50C Freescale Semiconductor, MC68030RC50C Datasheet - Page 479

• Manufacturer Part Number: MC68030RC50C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC50C

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

11-16
11.4 EFFECT OF DATA CACHE
the instruction may be minimized. Write accesses, however, always require
The effect of the data cache on operand read accesses can be factored into
the actual instruction execution time as follows.
When a data cache hit occurs for the data fetch corresponding to either the
fetch effective address table or the fetch immediate effective address table
When the data accesses required by an instruction are in the data cache,
in 11.6 INSTRUCTION TIMING TABLES, the following rules apply:
reading these operands requires no bus cycles, and the execution time for
bus cycles because the data cache is a w r i t e t h r o u g h cache.
Use the general Equation (11-2) to compute:
la. if T a i l t = 0 :
lb. if T a i l t = 1:
lc. if T a i l t > l :
Execution Time
.
This CC time is a m a x i m u m since the times given for the MULU.L
and DIVS.L are m a x i m u m s .
where:
time are calculated as for one data read.
If the EA mode is m e m o r y indirect (two data reads), the tail and CC
Tailt and CCt are the values listed in the tables.
= 2 + [44- min(2,0)] + [6- min(4,0)] + [14- min(6,2)] + [6-- min(6,0)] +
= 160 clock periods
= CCeal + [CCoPl - min(HoPl ,Teal )] + [CCea2 - min(Hea2,TOPl )] +
= 2 + 4 4 + 6 + 1 2 + 6 + 9 0
Tail = T a i l t - 1
CC = CCt - 1
Tail = T a i l t - (Tailt - 1 ) = 1
CC = C C t - ( T a i l t - 1)
[90 - rain(0,0)]
No change in timing.
[CCoP2- min(HoP2,Tea2) ] + [CCea 3 - min(Hea3,ToP2)] +
[CCoP3 - min(HoP3,Tea3) ]
MC68030 USER'S MANUAL
NOTE
MOTOROLA