MC68030RC50C Freescale Semiconductor, MC68030RC50C Datasheet - Page 538

• Manufacturer Part Number: MC68030RC50C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC50C

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
A0
/CPU
cycles and is derived from NANDing FC0-FC1 or FC0-FC2. The label, (addressb), is a designer-selectable
combination of address lines used to generate the proper address decode for the system's memory bank.
With the address lines given here the decode block size is 256K bytes. A similar address might be
PAL16L8
U1
MC68030 BYTE DATA SELECT GENERATION FOR 32-91T PORTS, MAPPED AND UNMAPPED.
MOTOROLA INC., AUSTIN, TEXAS
UUDA = RW
UMDA = RW
LMDA = RW
LLDA = RW
UUDB = RW */CPU * (addressb)
UMDB = RW*/CPU * (addressb)
LMDB = RW */CPU * (addressb)
LLDB = RW */CPU * (addressb)
DESCRIPTION: Byte select signals for writing. On
memory block is addressed. The Input signal/CPU prevents byte select assertion during CPU space
included in the equations for UUDA, UMDA, etc. if the designer wishes them to be memory mapped also.
+/A1 * SIZ0 * SlZl
+/,6,0 * A1 */CPU * (addressb)
+/A0 */A1
+ A0 */A1
+/A1 */SIZ0
+/A1 * SIZ1
+/A0 * A1
+/A1 */SlZ0 */SlZl
+/A1 * A0 */SIZ0
+ A 0 * A1
+ A0 * SIZ0 * SlZl
+/SIZ0 */SIZ1
+ A1 * SIZ1
+/A0 */A1 */CPU * (addressb)
+ A0 */A1 */CPU * (addressb)
+/A1 */SIZ0 */CPU * (eddressb)
+/A1 * SIZ1 */CPU * (addressb)
+/A1 */SIZ0 */SlZl */CPU * (addressb)
+/A1 * SIZ0 * SlZl */CPU * (addressb)
+/,6,1 * A0 */SIZ0 */CPU * (addressb)
+ A0 * A1 */CPU * (addressb)
+ A0 * SIZ0 * SIZ1 */CPU * (addressb)
+/SIZ0 */SIZ1 */CPU * (addressb)
+ A1 * SIZ1 */CPU * (addressb)
A1
/UUDA
/UMDA /LMDA
SIZ0
F i g u r e 12-7. N I C 6 8 0 3 0 B y t e S e l e c t P A L E q u a t i o n s
SIZ1
/LLDA
RW
MC68030 USER'S MANUAL
/UUDA /UMDB /LMDB /LLDB
A18
;word aligned, size is three byte
;enable upper byte on read of 32-bit port
;directly addressed, any size
;enable upper middle byte on read of 32-bit port
;directly addressed, any size
;word aligned, size byte or three byte
,'word aligned, size is word or long word
;enable lower middle byte on read of 32-bit port
;directly addressed, any size
;word aligned, size is long word
;word aligned, size is word or long word
;enable lower byte on read of 32-bit port
;directly addressed, any size
;odd alignment, three byte size
;size is long word, any address
;word aligned, word or three byte size
reads,
A19
;enable upper byte on read of 32-bit port
;directly addressed, any size
;enable upper middle byte on read of 32-bit port
;directly addressed, any size
,'word aligned, size byte or three byte
,'word aligned, size is word or long word
;enable lower middle byte on read of 32-bit port
;directly addressed, any size
,'word aligned, size is long word
;enable lower byte on read of 32-bit port
,'word aligned, size is three byte
,'word aligned, size is word or long word
;directly addressed, any size
;odd alignment, three byte size
;size is long word, any address
;word aligned, word or three byte size
all bytes selects are asserted if the respective
A20
A21
GND
VCC
12-13
12