MPC8347EVVALFB Freescale Semiconductor, MPC8347EVVALFB Datasheet - Page 91

• Manufacturer Part Number: MPC8347EVVALFB
• Description: IC MPU POWERQUICC II 672-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8347EVVALFB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 667MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 672-TBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 667MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 672
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.3V
• Operating Supply Voltage (max): 1.36V
• Operating Supply Voltage (min): 1.24V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: TBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8347E.
21.1
The MPC8347E includes two PLLs:
21.2
Each PLL gets power through independent power supply pins (AV
level should always equal to V
low frequency filter scheme.
There are a number of ways to provide power reliably to the PLLs, but the recommended solution is to
provide four independent filter circuits as illustrated in
Independent filters to each PLL reduce the opportunity to cause noise injection from one PLL to the other.
The circuit filters noise in the PLL resonant frequency range from 500 kHz to 10 MHz. It should be built
with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the
recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic
(Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value
capacitor.
To minimize noise coupled from nearby circuits, each circuit should be placed as closely as possible to the
specific AV
pin, which is on the periphery of package, without the inductance of vias.
Figure 42
Freescale Semiconductor
1. The platform PLL generates the platform clock from the externally supplied CLKIN input. The
2. The e300 core PLL generates the core clock as a slave to the platform clock. The frequency ratio
frequency ratio between the platform and CLKIN is selected using the platform PLL ratio
configuration bits as described in
between the e300 core clock and the platform clock is selected using the e300 PLL ratio
configuration bits as described in
System Clocking
PLL Power Supply Filtering
shows the PLL power supply filter circuit.
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11
DD
pin being supplied. It should be possible to route directly from the capacitors to the AV
V
DD
DD
Figure 42. PLL Power Supply Filter Circuit
10 Ω
, and preferably these voltages are derived directly from V
2.2 µF
Section 19.1, “System PLL Configuration.”
Section 19.2, “Core PLL Configuration.”
GND
Low ESL Surface Mount Capacitors
Figure
2.2 µF
42, one to each of the four AV
DD
AV
1, AV
DD
(or L2AV
DD
2, respectively). The AV
DD
)
System Design Information
DD
DD
through a
pins.
DD
DD
91