MPC8541EPXAQF Freescale Semiconductor, MPC8541EPXAQF Datasheet - Page 4

• Manufacturer Part Number: MPC8541EPXAQF
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIIr

Specifications of MPC8541EPXAQF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 1GHz
• Embedded Interface Type: I2C, SPI, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Rohs Compliant: No
• For Use With: MPC8548CDS - DEV TOOLS CDS FOR 8548CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Overview
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— SRAM operation supports relocation and is byte-accessible
— Cache mode supports instruction caching, data caching, or both
— External masters can force data to be allocated into the cache through programmed memory
— Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)
— Supports locking the entire cache or selected lines
— Global locking and flash clearing done through writes to L2 configuration registers
— Instruction and data locks can be flash cleared separately
— Read and write buffering for internal bus accesses
Address translation and mapping unit (ATMU)
— Eight local access windows define mapping within local 32-bit address space
— Inbound and outbound ATMUs map to larger external address spaces
DDR memory controller
— Programmable timing supporting first generation DDR SDRAM
— 64-bit data interface, up to MHz data rate
— Four banks of memory supported, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports
— Full ECC support
— Page mode support (up to 16 simultaneous open pages)
— Contiguous or discontiguous memory mapping
— Sleep mode support for self refresh DDR SDRAM
— Supports auto refreshing
— On-the-fly power management using CKE signal
— Registered DIMM support
— Fast memory access via JTAG port
— 2.5-V SSTL2 compatible I/O
Programmable interrupt controller (PIC)
— Programming model is compliant with the OpenPIC architecture
— Supports 16 programmable interrupt and processor task priority levels
— Supports 12 discrete external interrupts
— Supports 4 message interrupts with 32-bit messages
— Supports connection of an external interrupt controller such as the 8259 programmable
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
ranges or special transaction types (stashing).
– Individual line locks set and cleared through Book E instructions or by externally mastered
– Three inbound windows plus a configuration window on PCI
– Four inbound windows
– Four outbound windows plus default translation for PCI
interrupt controller
transactions
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