MC68040FE25A Freescale Semiconductor, MC68040FE25A Datasheet - Page 297
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MC68040FE25A
Manufacturer Part Number
MC68040FE25A
Description
IC MICROPROCESSOR 32BIT 184-CQFP
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68EC040FE33A.pdf
(442 pages)
Specifications of MC68040FE25A
Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
184-CQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
184
Package Type
CQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68040FE25A
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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The separation of calculation and execution in the <ea> calculate and execute stages
allows instruction reordering during compile time to take advantage of potential instruction
overlap. Figure 10-2 illustrates this overlap for an instruction requiring multiple clocks in
the execute stage and with an instruction with a long lead time. The execution time for
LEA (3
execution.
When the LEA (A) instruction precedes the ABCD (B) instruction, the execution stalls
during C4–C6 (equivalent to the LEA lead time) while the instruction completes in the
<ea> calculate and <ea> fetch stages. The resulting execution time for the LEA (A) and
ABCD (B) sequence is eight clocks.
However, if the LEA (C) instruction follows the ABCD (B) instruction, the LEA stalls in the
<ea> fetch instead, during C9–C11. The LEA then executes in a single clock in the
execution stage. The resulting execution time for the LEA (C) and ABCD (B) sequence is
five clocks.
10-6
L
+ 1) indicates that the instruction can be stalled three clocks without affecting
<ea> CALCULATE
NOTE: *Possible stalls in this stage.
WRITE-BACK
<ea> FETCH
EXECUTE
Figure 10-2. Instruction Overlap with Multiple Clocks
LABEL
P1
N1
N2
C1
P1
A
B
C
Freescale Semiconductor, Inc.
For More Information On This Product,
C2
P1
A
TRAPF
LEA
ABCD
LEA
TRAPF
TRAPF
INSTRUCTION
C3
P1
A
A
M68040 USER’S MANUAL
Go to: www.freescale.com
C4
$24(PC),A1
D0,D1
$24(PC),A1
A L
A
A
C5
A L
A
A
CALCULATE
C6
A L
B
A
<ea>
1
4
1
4
1
1
C7
C
B
A
C8
EXECUTE
C
C
B
3 L + 1
3 L + 1
1
3
1
1
C L1
C9
C
B
C10
C L2
C
B
C11
C L3
N1
C*
C12
N2
N1
C
C13
N2
N1
MOTOROLA
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