MC68040FE25A Freescale Semiconductor, MC68040FE25A Datasheet - Page 438

• Manufacturer Part Number: MC68040FE25A
• Description: IC MICROPROCESSOR 32BIT 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Explicit Bus Ownership, see Bus Arbitration
Extended Precision, see Data Format
External Bus Arbiter, 5-7, 5-10, 7-45, 7-46, 7-50,
EXTEST, 6-3, 6-12
F-line, A-6, B-10
Fetch Stage, see Integer Unit Pipeline
Floating-Point Exceptions, 1-8, 9-3
Floating-Point Pipeline, 9-1, 9-26
Floating-Point Registers
MOTOROLA
Bus Error, 3-22, 3-30, 4-12, 7-37, 7-42, 7-43,
Double Bus Fault, 7-43, 8-8, 8-18
F-Line, A-6, B-10
Format Error, 8-12, 8-28, 9-20
FTRAPcc, 9-20
Illegal Instruction, 8-9
Interrupt, 5-14, 7-29, 7-31, 8-12, 8-20
Memory Management Unit, 8-7
Priority, 8-19
Privilege Violation, 8-10
Reset, 5-11, 7-67, 7-68, 8-17
Trace, 8-10
Trap, 8-8, 8-20
Unimplemented Floating-Point Instruction, 1-2,
Unimplemented Instruction, 8-9
States
7-53, 7-55, 7-58
Arithmetic, 9-24
Branch/Set on Unordered (BSUN), 9-18,
Divide by Zero, 9-36
Floating-Point, 9-5
Inexact Result (INEX1 And INEX2), 9-24,
Multiple Exceptions, 9-25
Operand Error (OPERR), 9-28–9-31
Overflow Exception (OVFL), 9-16, 9-31–9-33,
Round-Off Error, 9-11
SNAN Exception, 9-27, 9-28
Underflow (UNFL), 9-16, 9-33–9-36, 9-42
Floating-Point Status Register (FPSR), 1-8,
9-21
9-20
9-25–9-27
9-36–9-38, 9-42
9-42
9-4, 9-15
AEXC Byte, 9-5; Setting the AEXC, 9-6
–F–
Freescale Semiconductor, Inc.
For More Information On This Product,
M68040 USER’S MANUAL
Go to: www.freescale.com
Floating-Point Registers
Floating-Point Registers
Floating-Point State Frames, 7-38, 9-39;
Floating-Point Unit (FPU), 1-2, 1-4
Floating-Point User Exception Handler
Floating-Point Vector Numbers, 9-20
Forced Rounding Precision, 9-13, 9-31, 9-34
Format Error, 8-12, 8-28, 9-20
Heat Sink, 11-29, 11-31
HIGHZ, 6-3, 6-12
IEEE Aware Tests, see Conditional Tests
IEEE Standard 1149.1, see JTAG
Implicit Bus Ownership, see Bus Arbitration
Indeterminate Condition, see Bus Arbitration
Indirect Descriptor, see Descriptors
Instruction Execution, 2-5
Instruction Timing, 10-1–10-36
Instruction Prefetches, 4-13
Floating-Point Control Register (FPCR), 1-8,
Floating-Point Data Register, 9-2, 9-15
Floating-Point Instruction Address Register
Field Definitions, 9-42, 9-43
Exception Handler, 9-5
Floating-Point State Frame, 7-38
Format $4 Stack Frame, A-5
Integer Pipeline, 10-29
Programming Model, 9-2
BSUN, 9-26
Divide by Zero, 9-36
INEX, 9-28, 9-30, 9-32, 9-33, 9-35, 9-37, 9-38
OPERR, 9-29, 9-30
OVFL, 9-32, 9-33
SNAN, 9-28
UNFL, 9-35
States
EXC Byte, 9-5, 9-13, 9-34, 9-37
FPCC Byte, 9-4
Quotient Byte, 9-5
9-3, 9-11, 9-18
ENABLE Byte, 9-3, 9-25; Encodings, 9-3
MODE Byte, 9-3, 9-31, 9-37
(FPIAR), 1-8, 9-6, 9-32, 9-35, 9-38
–H–
–I–
INDEX-3