MC68040RC33V Freescale Semiconductor, MC68040RC33V Datasheet - Page 213
MC68040RC33V
Manufacturer Part Number
MC68040RC33V
Description
IC MICROPROCESSOR 32BIT PGA-182
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68EC040FE33A.pdf
(442 pages)
Specifications of MC68040RC33V
Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
179-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
33MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
182
Package Type
PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Case 1
Case 2
MOTOROLA
If DLE is negated and meets setup time specification #35 to the rising edge of BCLK
when the bus read is terminated, latch A is transparent, and the read data must meet
setup and hold time specifications #36 and #37 to the rising edge of BCLK. Read timing
is similar to normal timing for this case.
If DLE is asserted, the data bus levels are latched and held internally. D31–D0 must
meet setup and hold time specifications #32 and #33 to the falling edge of DLE, and can
transition to a new level once DLE is asserted. D31–D0 must still meet setup time
specification #36 to BCLK, but not hold time specification #37, since the data is
internally held valid as long as DLE remains asserted low.
D0–D31 IN
(READ)
BCLK
DLE
TA
Figure 7-48. DLE versus Normal Data Read Timing
Freescale Semiconductor, Inc.
36
For More Information On This Product,
35
D0–D31 IN
CASE 1
(READ)
BCLK
Go to: www.freescale.com
M68040 USER’S MANUAL
TA
37
DLE MODE DATA BUS TIMING
NORMAL DATA BUS TIMING
15
32
16
31
CASE 2
36
33
34
7- 71
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