MC68040RC33V Freescale Semiconductor, MC68040RC33V Datasheet - Page 43

• Manufacturer Part Number: MC68040RC33V
• Description: IC MICROPROCESSOR 32BIT PGA-182
• Manufacturer: Freescale Semiconductor

Specifications of MC68040RC33V

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 179-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 182
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

An instruction stream is fetched from the instruction memory unit and decoded on an
instruction-by-instruction basis in the decode stage. Multiple instructions are fetched to
keep the pipeline stages full so that the pipeline will not stall.
The decoded instruction is then passed to the <ea> calculate stage to calculate the
effective addresses that the instruction requires. The <ea> calculate stage initiates
additional fetches from the instruction stream to obtain the effective address extension
words and performs the effective address calculation. The initial execution of the
instruction in the execute stage handles any data registers required for the calculation,
which passes the register back to the <ea> calculate stage.
The resulting effective address is passed to the <ea> fetch stage, which initiates an
operand fetch from the data memory controller if the effective address is for a source
operand. The fetched operand is returned to the execute stage, which completes
execution of the instruction and writes any result to either a data register, memory, or back
to the <ea> calculate stage for storage in an address register. For a memory destination,
the <ea> fetch stage passes the address to the execution stage.
The previously described sequence of effective address calculation and fetch can occur
multiple times for an instruction, depending on the source and/or destination addressing
modes. For memory indirect addressing modes, the <ea> calculate stage initiates an
operand fetch from the intermediate indirect memory address, then calculates the final
2-2
Freescale Semiconductor, Inc.
SHADOW
SHADOW
TO FPU
For More Information On This Product,
Figure 2-1. Integer Unit Pipeline
M68040 USER’S MANUAL
Go to: www.freescale.com
FROM CACHE OR BUS
INSTRUCTION DATA
<ea> CALCULATE
INSTRUCTION
CONTROLLER
WRITE-BACK
<ea> FETCH
EXECUTE
DECODE
FETCH
TO CACHE OR
BUS CONTROLLER
TO CACHE OR
BUS CONTROLLER
MOTOROLA