MPC8572EPXAVND Freescale Semiconductor, MPC8572EPXAVND Datasheet - Page 124

• Manufacturer Part Number: MPC8572EPXAVND
• Description: MPU POWERQUICC III 1023-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8572EPXAVND

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.5GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

System Design Information
21.2
21.2.1
Each of the PLLs listed above is provided with power through independent power supply pins
(AV
AV
voltages are derived directly from V
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits per PLL power supply as illustrated in
AV
one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of the 1023 FC-PBGA footprint, without the inductance of vias.
Figure 62
The AV
of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in
following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the
AV
the AV
capacitors, and finally the 1 Ω resistor to the board supply plane. The capacitors are connected from
124
DD
DD
DD
DD
_SRDS2 respectively). The AV
_SRDSn ball to ensure it filters out as much noise as possible. The ground connection should be near
pins. By providing independent filters to each PLL the opportunity to cause noise injection from
_PLAT, AV
DD
DD
Power Supply Design
_SRDSn ball. The 0.003-µF capacitor is closest to the ball, followed by the two 2.2 µF
shows the PLL power supply filter circuits.
_SRDSn signal provides power for the analog portions of the SerDesn PLL. To ensure stability
PLL Power Supply Filtering
It is recommended to have the minimum number of vias in the AV
for board layout. For example, zero vias might be possible if the AV
is placed on the component side. One via might be possible if it is placed on
the opposite of the component side. Additionally, all traces for AV
the filter components should be low impedance, 10 to 15 mils wide and
short. This includes traces going to GND and the supply rails they are
filtering.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
DD
V
_CORE0, AV
DD
10 Ω
Figure 62. PLL Power Supply Filter Circuit
DD
DD
DD
_CORE1, AV
through a low frequency filter scheme such as the following.
2.2 µF
level should always be equivalent to V
GND
NOTE
DD
Low ESL Surface Mount Capacitors
_DDR, AV
2.2 µF
DD
AV
DD
_LBIU, AV
DD
pin being supplied to minimize
Figure
DD
DD
62, one to each of the
DD
DD
DD
, and preferably these
_SRDS1 and
Freescale Semiconductor
trace
filter
and
DD