MPC8572ECVTAULD Freescale Semiconductor, MPC8572ECVTAULD Datasheet - Page 52

• Manufacturer Part Number: MPC8572ECVTAULD
• Description: MPU POWERQUICC III 1023-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8572ECVTAULD

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Ethernet Management Interface Electrical Characteristics
Figure 28
52
At recommended operating conditions with LV
ECn_MDIO to ECn_MDC hold time
ECn_MDC rise time
ECn_MDC fall time
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. This parameter is dependent on the eTSEC system clock speed, which is half of the Platform Frequency (f
3. The maximum ECn_MDC output clock frequency is defined based on the maximum platform frequency for MPC8572E
4. Guaranteed by design.
5. t
(reference)(state)
symbolizes management data timing (MD) for the time t
invalid (X) or data hold time. Also, t
signals (D) reach the valid state (V) relative to the t
rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
ECn_MDC output clock frequency for a specific eTSEC port can be programmed by configuring the MgmtClk bit field of
MPC8572E’s MIIMCFG register, based on the platform (CCB) clock running for the device. The formula is: Platform
Frequency (CCB)/(2*Frequency Divider determined by MIICFG[MgmtClk] encoding selection). For example, if
MIICFG[MgmtClk] = 000 and the platform (CCB) is currently running at 533 MHz, f
That is, for a system running at a particular platform frequency (f
programmed between maximum f
MIIMCFG register section for more detail.
(600 MHz) divided by 64, while the minimum ECn_MDC output clock frequency is defined based on the minimum platform
frequency for MPC8572E (400 MHz) divided by 448, following the formula described in Note 2 above. The typical
ECn_MDC output clock frequency of 2.5 MHz is shown for reference purpose per IEEE 802.3 specification.
plb_clk
Parameter/Condition
is the platform (CCB) clock.
shows the MII management AC timing diagram.
ECn_MDIO
ECn_MDIO
ECn_MDC
for inputs and t
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
(Output)
(Input)
Table 45. MII Management AC Timing Specifications (continued)
Figure 28. MII Management Interface Timing Diagram
(first two letters of functional block)(reference)(state)(signal)(state)
MDC
MDDVKH
t
MDCH
DD
Symbol
= f
t
/TV
MDDXKH
t
t
t
MDDVKH
MDCR
MDHF
CCB
DD
t
MDC
symbolizes management data timing (MD) with respect to the time data input
/64 and minimum f
of 3.3 V ± 5% or 2.5 V ± 5%.
t
MDKHDX
1
MDC
MDC
clock reference (K) going to the high (H) state or setup time. For
Min
—
—
0
from clock reference (K) high (H) until data outputs (D) are
t
MDCF
MDC
CCB
= f
), the ECn_MDC output clock frequency can be
t
MDDXKH
CCB
(first two letters of functional block)(signal)(state)
Typ
—
—
—
/448. Refer to MPC8572E reference manual’s
t
MDCR
MDC
for outputs. For example, t
= 533/(2*4*8) = 533/64 = 8.3 MHz.
Max
10
10
—
Freescale Semiconductor
Unit
ns
ns
ns
CCB
). The actual
MDKHDX
Notes
—
4
4