MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 153

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

When the user INEX exception handler has completed, the floating-point frame may be dis-
carded. The RTE instruction must be executed to return to normal instruction flow.
6.7 FLOATING-POINT STATE FRAMES
All floating-point arithmetic exception handlers must have FSAVE as the first floating-point
instruction; any other floating-point instruction causes another exception to be reported.
Once the FSAVE instruction has executed, the exception handler should use only the
FMOVEM instruction to read or write to the floating-point data registers since FMOVEM can-
not generate further exceptions or change the FPCR.
An FSAVE instruction is executed to save the current floating-point internal state for context
switches and floating-point exception handling. When an FSAVE is executed, the processor
waits until the FPU either completes the instruction or is unable to perform further process-
ing due to a pending exception that must be serviced.
FSAVE operations always write a floating-point state frame containing three long words.
The exception operand, is part of the EXCP frame. This exception operand retains its value
when FRESTOREd as an EXCP frame into the processor and then FSAVEd at a later time.
The FSAVE frame contents are shown in Figure 6-10 and the status word contents are
shown in Figure 6-11.
Bits 15–8 of the first long word of the floating-point frame define the frame format. The legal
formats for the MC68060 are:
MOTOROLA
$00
$60
$E0
The IEEE 754 standard specifies that inexactness should be sig-
naled on overflow as well as for rounding. The processor imple-
ments this via the INEX bit in the FPSR AEXC byte. However,
the standard also indicates that the inexact exception should be
taken if an overflow occurs with the OVFL bit disabled and the
INEX bit enabled in the FPSR AEXC byte. Therefore, the pro-
cessor takes the inexact exception if this combination of condi-
tions occurs, even though the INEX1 or INEX2 bit may not be set
in the FPSR EXC byte. In this case, the INEX bit is set in the
FPSR AEXC byte, and the OVFL bit is set in both the FPSR EXC
and AEXC bytes.
Null Frame (NULL)
Idle Frame (IDLE)
Exception Frame (EXCP)
31
EXCP Operand Exponent
Figure 6-10. Floating-Point State Frame
M68060 USER’S MANUAL
EXCP Operand Lower 32 bits
EXCP Operand Upper 32 bits
NOTE
16
15
Status Word
Floating-Point Unit
0
6-35