MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 297
MC68LC060RC66
Manufacturer Part Number
MC68LC060RC66
Description
IC MPU 32BIT 66MHZ 206-PGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68060RC50.pdf
(416 pages)
Specifications of MC68LC060RC66
Processor Type
M680x0 32-Bit
Speed
66MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
206-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
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SECTION 10
INSTRUCTION EXECUTION TIMING
This section details the MC68060 instruction execution times in terms of processor clock
cycles and the superscalar architecture. The number of operand cycles for each instruction
is also included, enclosed in parentheses following the number of clock cycles. Timing
entries are presented as:
where:
10.1 SUPERSCALAR OPERAND EXECUTION PIPELINES
The superscalar architecture of the MC68060 processor consists of three structures within
the operand execution pipeline (OEP). The components include a primary OEP (pOEP), a
secondary OEP (sOEP) plus a monolithic register file containing the general-purpose regis-
ters, Dn and An. As instructions are gated out of the instruction fetch pipeline’s instruction
buffer, consecutive operation words (if available) are loaded into the pOEP and sOEP. A
superscalar instruction dispatch algorithm must then determine if the instruction-pair may
continue its OEP execution simultaneously.
Each OEP consists of two compute engines: an adder structure for calculating operand vir-
tual addresses (the address generation unit (AGU)) and an integer execute engine for per-
forming instruction operations (the integer execute engine (IEE)).
MOTOROLA
r/w = The number of operand reads (r) and writes (w). A read-modify-write cycle is
C = The number of processor clock cycles, including all applicable operand fetches and
stores, plus all internal CPU cycles required to complete the instruction execution.
denoted as (1/1).
M68060 USER’S MANUAL
C(r/w)
10-1
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