TS68040VR25A Atmel, TS68040VR25A Datasheet - Page 7

• Manufacturer Part Number: TS68040VR25A
• Description: IC MPU 32BIT 25MHZ 179PGA
• Manufacturer: Atmel

Specifications of TS68040VR25A

• Processor Type: 68000 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 179-PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Table 3. Signal Index
2116A–HIREL–09/02
Signal Name
Address Bus
Data Bus
Transfer Type
Transfer Modifier
Transfer Line Number
User Programmable Attributes
Read Write
Transfer Size
Bus Lock
Bus Lock End
Cache Inhibit Out
Transfer Start
Transfer in Progress
Transfer Acknowledge
Transfer Error Acknowledge
Transfer Cache Inhibit
Transfer Burst Inhibit
Data Latch Enable
Snoop Control
Memory Inhibit
Bus Request
Bus Grant
Bus Busy
Cache Disable
MMU Disable
Reset In
Reset Out
Interrupt Priority Level
Interrupt Pending
Autovector
Processor Status
TLN1, TLN0
PST3-PST0
Mnemonic
SIZ1, SIZ0
TM2, TM0
SC1, SC0
IPL2-IPL0
TT1, TT0
D31-D0
LOCKE
A31-A0
CIOUT
IPEND
UPA1,
LOCK
RSTO
AVEC
UPA0
MDIS
CDIS
RSTI
R/W
TEA
DLE
TIP
TCI
TBI
BR
BG
TS
TA
BB
MI
Function
32-bit address bus used to address any of 4G bytes
32-bit data bus used to transfer up to 32 bits of data per bus transfer
Indicates the general transfer type: normal, MOVE 16, alternate logical function
code, and acknowledge
Indicates supplemental information about the access
Indicates which cache line in a set is being pushed or loaded by the current line
transfer
User-defined signals, controlled by the corresponding user attribute bits from the
address translation entry
Identifies the transfer as a read or write
Indicates the data transfer size. These signals, together with A0 and A1, define the
active sections of the data bus
Indicates a bus transfer is part of a read-modify-write operation, and that the
sequence of transfers should not be interrupted
Indicates the current transfer is the last in a locked sequence of transfer
Indicates the processor will not cache the current bus transfer
Indicates the beginning of a bus transfer
Asserted for the duration of a bus transfer
Asserted to acknowledge a bus transfer
Indicates an error condition exists for a bus transfer
Indicates the current bus transfer should not be cached
Indicates the slave cannot handle a line burst access
Alternate clock input used to latch input data when the processor is operating in
DLE mode
Indicates the snooping operation required during an alternate master access
Inhibits memory devices from responding to an alternate master access during
snooping operations
Asserted by the processor to request bus mastership
Asserted by an arbiter to grant bus mastership to the processor
Asserted by the current bus master to indicate it has assumed ownership of the bus
Dynamically disables the internal caches to assist emulator support
Disables the translation mechanism of the MMUs
Processor reset
Asserted during execution of the RESET instruction to reset external devices
Provides an encoded interrupt level to the processor
Indicates an interrupt is pending
Used during an interrupt acknowledge transfer to request internal generation of the
vector number
Indicates internal processor status
TS68040
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