TSPC603RVGH10LC Atmel, TSPC603RVGH10LC Datasheet - Page 39

• Manufacturer Part Number: TSPC603RVGH10LC
• Description: IC MPU 32BIT 10MHZ 255CBGA
• Manufacturer: Atmel

Specifications of TSPC603RVGH10LC

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 233MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 255-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Table 12-2.
5410B–HIREL–09/05
Exception Type
DSI
ISI
External interrupt
Alignment
Exceptions and Conditions (Continued)
Vector Offset
00300
00400
00500
00600
(hex)
Causing Conditions
The cause of a DSI exception can be determined by the bit settings in the DSISR, listed as
follows:
1 Set if the translation of an attempted access is not found in the primary hash table entry
group (HTEG), or in the rehashed secondary HTEG, or in the range of the DBAT register;
otherwise cleared
4 Set if a memory access is not permitted by the page or DBAT protection mechanism;
otherwise cleared
5 Set by an eciwx or ecowx instruction if the access is to an address that is marked as
write-through, or execution of a load/store instruction that accesses a direct-store segment
6 Set for a store operation and cleared for a load operation
11 Set if eciwx or ecowx is used and EAR[E] is cleared
An ISI exception is caused when an instruction fetch cannot be performed for any of the
following reasons:
An external interrupt is caused when MSR[EE] = 1 and the INT signal is asserted
An alignment exception is caused when the 603e cannot perform a memory access for any
of the reasons described below:
• The effective (logical) address cannot be translated. That is, there is a page
• The fetch access violates memory protection. If the key bits (Ks and Kp) in the
• The operand of a floating-point load or store instruction is not word-aligned
• The operand of lmw, stmw, lwarx, and stwcx, instructions are not aligned
• The operand of a single-register load or store operation is not aligned, and the
• The instruction is lmw, stmw, lswi, lwsx, stswi, stswx and the 603e is in little-
• The operand of dcbz is in storage that is write-through-required, or caching
fault for this portion of the translation, so an ISI exception must be taken to load
the PTE (and possibly the page) into memory
segment register and the PP bits in the PTE are set to prohibit read access,
instructions cannot be fetched from this location
603e is in little-endian mode
endian mode
inhibited
TSPC603R
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