668-0010 Rabbit Semiconductor, 668-0010 Datasheet - Page 156
668-0010
Manufacturer Part Number
668-0010
Description
IC MPU RABIT3000 55.5MHZ 128LQFP
Manufacturer
Rabbit Semiconductor
Datasheet
1.20-668-0011.pdf
(312 pages)
Specifications of 668-0010
Rohs Status
RoHS non-compliant
Processor Type
Rabbit 3000 8-Bit
Speed
55.5MHz
Voltage
2.5V, 2.7V, 3V, 3.3V
Mounting Type
Surface Mount
Package / Case
128-LQFP
Features
-
Other names
316-1016
- Current page: 156 of 312
- Download datasheet (2Mb)
Several types of data encoding are available in the HDLC mode. In addition to the normal
NRZ, they are NRZI, biphase-level (Manchester), biphase-space (FM0), and biphase-
mark (FM1). Examples of these encodings are shown below. Note that the signal level
does not convey information in NRZI, biphase-space, and biphase-mark. Instead it is the
placement of the transitions that determine the data. In biphase-level it is the polarity of
the transition that determines the data.
Figure 18-1. Examples of Data Encoding In the HDLC Mode
In the HDLC mode the internal clock comes from the output of Timer A2/Timer A3. The
timer output is divided by 16 to form the transmit clock, and is fed to the digital phase-
locked loop (DPLL) to form the receive clock. The DPLL is basically just a divide-by-16
counter that uses the timing of the transitions on the receive data stream to adjust its count.
The DPLL adjusts the count so that the DPLL output will be properly placed in the bit
cells to sample the receive data. To work properly, then, transitions are required in the
receive data stream. NRZ data encoding does not guarantee transitions in all cases (a long
string of zeros, for example), but the other data encodings do. NRZI guarantees transitions
because of the inserted zeros, and the biphase encodings all have at least one transition per
bit cell.
The DPLL counter normally counts by 16, but if a transition occurs earlier or later than
expected, the count will be modified during the next count cycle. If the transition occurs
earlier than expected, it means that the bit cell boundaries are early with respect to the
DPLL-tracked bit-cell boundaries, so the count is shortened by either one or two counts. If
the transition occurs later than expected, it means that the bit-cell boundaries are late with
146
Rabbit 3000 Microprocessor User’s Manual
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