668-0010 Rabbit Semiconductor, 668-0010 Datasheet - Page 157
668-0010
Manufacturer Part Number
668-0010
Description
IC MPU RABIT3000 55.5MHZ 128LQFP
Manufacturer
Rabbit Semiconductor
Datasheet
1.20-668-0011.pdf
(312 pages)
Specifications of 668-0010
Rohs Status
RoHS non-compliant
Processor Type
Rabbit 3000 8-Bit
Speed
55.5MHz
Voltage
2.5V, 2.7V, 3V, 3.3V
Mounting Type
Surface Mount
Package / Case
128-LQFP
Features
-
Other names
316-1016
- Current page: 157 of 312
- Download datasheet (2Mb)
respect to the DPLL-tracked bit-cell boundaries, so the count is lengthened by either one
or two counts. The decision to adjust by one or by two depends on how far off the DPLL-
tracked bit cell boundaries are. This tracking allows for minor differences in the transmit
and receive clock frequencies.
With NRZ and NRZI data encoding, the DPLL counter runs continuously, and adjusts
after every receive data transition. Since NRZ encoding does not guarantee a minimum
density of transitions, the difference between the sending data rate and the DPLL output
clock rate must be very small, and depends on the longest possible run of zeros in the
received frame. NRZI encoding guarantees at least one transition every six bits (with the
inserted zeros). Since the DPLL can adjust by two counts every bit cell, the maximum dif-
ference between the sending data rate and the DPLL output clock rate is 1/48 (~2%).
With biphase data encoding (either biphase-level, biphase-mark, or biphase-space), the
DPLL runs only as long as transitions are present in the receive data stream. Two consecu-
tive missed transitions causes the DPLL to halt operation and wait for the next available
transition. This mode of operation is necessary because it is possible for the DPLL to lock
onto the optional transitions in the receive data stream. Since they are optional, they will
eventually not be present, and the DPLL can attempt to lock onto the required transitions.
Since the DPLL can adjust by one count every bit cell, the maximum difference between
the sending data rate and the DPLL output clock rate is 1/16 (~6%).
With biphase data encoding, the DPLL is designed to work in multiple-access conditions
where there might not be flags on an idle line. The DPLL will generate an output clock
correctly based on the first transition in the leading zero of an opening flag. Similarly, only
the completion of the closing flag is necessary for the DPLL to provide the extra two
clocks to the receiver to assemble the data correctly. The transition is specified as follows.
• In the biphase-level mode this means the transition that defines the last zero of the
• In the biphase-mark and the biphase-space modes this means the transition that defines
Chapter 18 Serial Ports E – F
closing flag.
the end of the last zero of the closing flag.
147
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