668-0010 Rabbit Semiconductor, 668-0010 Datasheet - Page 275

• Manufacturer Part Number: 668-0010
• Description: IC MPU RABIT3000 55.5MHZ 128LQFP
• Manufacturer: Rabbit Semiconductor

Specifications of 668-0010

• Rohs Status: RoHS non-compliant
• Processor Type: Rabbit 3000 8-Bit
• Speed: 55.5MHz
• Voltage: 2.5V, 2.7V, 3V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Features: -
• Other names: 316-1016

Since its release, the Rabbit 3000 microprocessor has gone through one revision. The revi-
sion reflects bug fixes, improvements, and the introduction of new features. All Rabbit
3000 revisions are pin-compatible, and transparently replace previous versions of the chip.
The Rabbit 3000 has been supplied in the following versions.
1. Original Rabbit 3000—Available in two packages and identified by IL1T for the
Appendix B Rabbit 3000 Revisions
LQFP package and IZ1T for the TFBGA package. The LQFP package began shipping
in March 2002, and the TFBGA package began shipping in January 2003. There were
several bugs:
(a) Port A decode bug—This bug is documented in Rabbit’s Technical Note
(b) LDIR/LDDR with wait states—A new
(c) Interrupt after I/O with Short /CSx enabled—When the short chip select option
A
TN228, Rabbit 3000 Parallel Port F Bug. The problem involves an incom-
plete address decode of the data output register for Parallel Port A. If Parallel
Port A is used as an output or is used as the bidirectional bus for the slave port,
then writing to any of the Parallel Port F registers will cause a spurious write to
the Parallel Port A register.
September, 2002. The problem has to do with wait states and the block move
operations. With this problem, the first iteration of
number of wait states for both the read and the write. However, all subsequent
iterations use the number of waits programmed for the memory located at the
write address for both the read and the write cycles. This becomes a problem
when moving a block of data from a slow memory device requiring wait states
to a fast memory device requiring no wait states. With respect to external I/O
operations, the
of the waits programmed for the I/O for all but the first iteration. The first iter-
ation is correct. This bug is automatically corrected by Dynamic C, and was
fixed in future generations of the chip.
is enabled, the interrupt sequence will attempt to write the return address to the
stack if an interrupt takes place immediately after an internal or an external I/O
instruction. The chip select will be suppressed during the write cycle, and the
correct return address will not be stored on the stack. This happens only when
an interrupt takes place immediately after an I/O instruction when the short
chip select option is enabled.
PPENDIX
LDIR
B. R
or
LDDR
performs reads with zero wait states independent
ABBIT
LDIR/LDDR
3000 R
LDIR/LDDR
bug was discovered in
EVISIONS
uses the correct
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