GCIXP1240AC Intel, GCIXP1240AC Datasheet - Page 16

• Manufacturer Part Number: GCIXP1240AC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1240AC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 837152

Intel
Errata
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Problem:
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16
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IXP1240 Network Processor
PCI_OUT_INT_MASK Register Bits Not Readable
PCI Out Interrupt Mask register at 34h. The register is write only and cannot be read back.
The mask is operational, but the only way to test it is by generating I
PCI, writing 1 to this register, and then checking if subsequent interrupts to PCI are masked.
None.
Fixed
Spurious PCI Parity Errors
After initialization, the IXP1240 may indicate spurious PCI parity errors until at least 32 longwords
have been transferred to the PCI bus using a target read mechanism.
PCI parity errors may occur in the first 32 longwords during a target read.
The PCI bus initialization logic should include a 32 longword (or more) target read operation to
each IXP1240. During this interval, ignore PCI parity errors.
NoFix
SDRAM Arbiter
Commands are dropped in the SDRAM controller when using
Chip would “hang” due to a lockout condition in the SDRAM arbiter A specific sequence of
DRAM commands to different queues would eventually cause the arbiter to NOT grant any
command that isn’t intended for the high priority queue.
Using the optimize_mem token on SDRAM references may freeze microengines
Don’t use opt_mem queue with SDRAM references
Fixed
Problem with CRC
Problem with CRC when data not is not 64-bit aligned.
CRC calculation over unaligned data from DRAM to TFIFO was not calculated correctly. Data was
also not making it to the TFIFO correctly. The problems occurred with and without CRC masking,
and on all burst sizes.
Requires additional instructions to align data, thus preventing ATM OC12 speed.
None
Fixed
SDRAM_CRC
SDRAM_CRC instruction hangs the IXP1240.
The IXP1240 appears to hang while doing sdram[read], read_crc. The problem here is that during
an SDRAM chain, a non-DRAM instruction would interleave itself on the command bus right
before the last SDRAM reference in the chain. This caused the chain reference to stop and the last
sdram reference (which had a ctx_swap token) would not go into the ordered queue. So the chain is
sitting there waiting for the last reference, which will never arrive, and the ctx_swap would never
return because its instruction will never get out of the queue.
Can’t use CRC.
sdram[],
optimize_mem
2
0 and doorbell interrupts to
Specification Update