GCIXP1240AC Intel, GCIXP1240AC Datasheet

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... Dual DMA channels Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Datasheet Industry Standard 64-bit SDRAM Interface — ...

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... Information in this document is provided in connection with Intel property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right ...

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... Miscellaneous Test Pins.........................................................................42 3.3.11 Pin Usage Summary ..............................................................................43 3.4 Pin/Signal List......................................................................................................44 3.5 Signals Listed in Alphabetical Order ...................................................................48 3.6 IX Bus Pins Function Listed by Operating Mode.................................................52 3.7 IX Bus Decode Table Listed by Operating Mode Type .......................................62 3.8 Pin State During Reset........................................................................................64 Datasheet ® Intel IXP1240 Network Processor iii ...

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... Intel IXP1240 Network Processor 3.9 Pullup/Pulldown and Unused Pin Guidelines ...................................................... 66 4.0 Electrical Specifications ................................................................................................... 67 4.1 Absolute Maximum Ratings ................................................................................ 67 4.2 DC Specifications................................................................................................ 70 4.2.1 Type 1 Driver DC Specifications ............................................................ 70 4.2.2 Type 2 Driver DC Specifications ............................................................ 71 4.2.3 Overshoot/Undershoot Specifications .................................................... 71 4.3 AC Specifications ................................................................................................ 72 4.3.1 Clock Timing Specifications ................................................................... 72 4.3.2 PXTAL Clock Input................................................................................. 72 4 ...

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... Unidirectional IX Bus Timing - Consecutive Receives, EOP on 16th Data Return with Status ....................................................................................101 40 32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP on 15th Data Return with Status ....................................................................................102 41 32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP on 14th Data Return with Status ....................................................................................103 Datasheet ® Intel IXP1240 Network Processor v ...

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... Intel IXP1240 Network Processor 42 32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP on 1st Through 13th Data Return with Status (13th Data Return Shown) ................... 104 43 32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP, 64-Bit Status ................................................................................................................ 105 44 32-Bit Unidirectional IX Bus Timing - Consecutive Receives, Two Element Transfers with 32-Bit Status ...

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... Pin State During Reset........................................................................................64 31 Absolute Maximum Ratings.................................................................................67 32 Functional Operating Range ...............................................................................68 33 Typical and Maximum Power ..............................................................................68 34 Maximum and Typical Bus Loading Used for the Power Calculations ................68 35 I1, I3, O1, O3, O4, and O5 Pin Types .................................................................70 Datasheet ® Intel IXP1240 Network Processor vii ...

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... Intel IXP1240 Network Processor 36 I2 and O2 Pin Types ........................................................................................... 71 37 Overshoot/Undershoot Specifications................................................................. 71 38 PXTAL Clock Inputs ............................................................................................ MHz PCI Clock Signal AC Parameters .......................................................... MHz PCI Clock Signal AC Parameters .......................................................... MHz PCI Signal Timing .................................................................................. MHz PCI Signal Timing .................................................................................. 75 42 Reset Timings Specification................................................................................ 76 43 IEEE 1149.1/Boundary-Scan Interface Timing ................................................... 79 44 FCLK Signal AC Parameter Measurements ...

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... GPIO RTC SRAM Unit Micro- engine 1 FBI Unit Scratchpad Memory (4 Kbyte) Hash Unit IX Bus Interface Micro- engine 4 Intel IXP1240 Network Processor ® Intel IXP1240 Network Processor PCI Unit 32-bit bus 64-bit bus SDRAM Unit Micro- Micro- engine engine 2 3 Micro- Micro- ...

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... Figure 2. System Block Diagram SSRAM (8 Mbytes Max) Buffer BootROM (8 Mbytes Max) SlowPort Devices (2 Mbytes Max PCI Bus (33-66Mhz) 32 Control ® Intel Data 32 IXP1240 r Processo 64 IX Bus Data Control and Status Network Interface Devices Network Command SDRAM (256 Mbytes 64 Data Max) JTAG ...

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... V4.0 Architecture Reference typically refer to a word as being equal to 32 bits, and a halfword as being equal to 16 bits. 2.2 StrongARM* Core The StrongARM* core is the same industry standard 32-bit RISC processor as used in the Intel * StrongARM SA-1100 compatible with the StrongARM* processor family currently used in applications such as network computers, PDAs, palmtop computers and portable telephones ...

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... Intel IXP1240 Network Processor 2.4 FBI Unit and the IX Bus The FBI Unit is responsible for servicing fast peripherals, such as MAC-layer devices, on the IX Bus. This includes moving data to and from the IXP1240 Receive and Transmit FIFOs. The IX Bus provides a 4.4 Gbps interface to peripheral devices. The IX Bus was specifically designed to provide a simple and efficient interface ...

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... Table 26 tri-state. The IX Bus and Intel devices using the IX Bus, such as the 21440 and IXF1002, observe a pipelined bus protocol. When receive transfers are terminated early, the pipeline continues to cause several extra bus cycles depending on when the EOP signal was asserted. Data is a “don't care” for these trailing bus cycles, except in the case of a status transfer where the IX Bus burst includes a possible status transfer if the device were programmed to support it ...

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... Intel IXP1240 Network Processor Table 4. 32-bit IX Bus Receive Remainder Cycles, with Status Transfer 32-bit status Status transfer 64-bit status # of Don’t Care cycles: NOTE: 1. Status transfer occurs on one or two subsequent IX Bus cycles. In both 32-bit and 64-bit modes, all of the associated FBE_L signals (FBE_L[7:4] in 32-bit mode and FBE_L[7:0] for 64-bit mode) are driven low on a transmit ...

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... Transmit and Receive FIFOs in the FBI Unit. Refer to the IXP1200 Network Processor Family Hardware Reference Manual for details on how these requests are queued, prioritized, and serviced by the SDRAM Unit. SDRAM should have an access time (t Datasheet ® Intel IXP1240 Network Processor ) less (CAS latency = 2), PC100 compatible providing a peak core ...

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... Intel IXP1240 Network Processor Figure 3 details the major components of the SDRAM Unit. Figure 3. SDRAM Unit Block Diagram WE_L,RAS_L CAS_L, DQM SDRAM up to 256 MB Addr[14:0] Data[63:0] SDCLK * Other names and brands may be claimed as the property of others. ** ARM architecture compatible The SDRAM Bus consists of 15 row/column address bits, 64 data bits, RAS_L, CAS_L, write enable, DQM control, and a synchronous output clock running at one-half the IXP1240 core frequency (0 ...

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... Table 5. SDRAM CRC Types CRC Type X CRC-32 +X CRC-16 X CRC-10 x Datasheet Table 5. Polynomial +X +x+1 ® Intel IXP1240 Network Processor Application Bit Order 10 8 ATM AAL5 MSB first +X Ethernet LSB first HDLC LSB first Frame Relay LSB first MSB first, ATM OAM LW (or LW +1) 17 ...

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... Intel IXP1240 Network Processor 2.5.4 SDRAM Configurations Table 6. SDRAM Configurations Total Number of Memory Chips 8 Mbytes 4 16 Mbytes 8 32 Mbytes 4 64 Mbytes 8 32 Mbytes 4 64 Mbytes 8 64 Mbytes 4 128 Mbytes 8 128 Mbytes 4 256 Mbytes 8 2.5.5 SRAM Unit The IXP1240 provides an SRAM Unit for very high bandwidth memory for storage of lookup tables and other data for the packet processing Microengines ...

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... SCED values specify the RD/WR and Chip Enable signal assert and deassert times. When the I/O cycles begins, the SCC value is loaded into the internal state counter and is decremented on each Datasheet ® Intel IXP1240 Network Processor Service Priority (Arbitration) Machine & Registers ...

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... Intel IXP1240 Network Processor core clock tick (twice the SCLK frequency). When the state counter reaches the RDY_L Pause State Value, it will remain in that state until the HIGH_EN_L pin is sampled LOW, allowing the state counter to resume its decrement operation. The HIGH_EN_L must be driven for at least two SCLK periods to be sampled properly by the IXP1240 ...

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... Bit write accesses result in Read-Modify-Write cycles. — Unlike the StrongARM* core, the Microengine microinstruction allows you to perform bit operations within the instruction (Push, Pop, Bit Test and Set, CAM operations, Lock/Unlock, etc.). Datasheet ® Intel Number of Chips Size of Boot ROM (Maximum Mbit ...

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... PCI devices are supported only, the IXP1240 and a second PCI device. To increase the number of PCI devices supported or to add connectors to the bus at the higher PCI Bus speeds, a PCI-to-PCI bridge device, such the Intel 21150, 21152, or 21153 is required. Both PCI Initiator and Target cycles are supported target device, the IXP1240 responds as a Medium Speed device asserting DEVSEL_L two PCI_CLK cycles after FRAME_L is asserted ...

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... Hardware Reset via RESET_IN_L pin • Software Reset by StrongARM* core or by PCI device write to the IXP1200_RESET register • PCI Reset via the PCI_RST_L pin • Watchdog Timer expiration Figure 5 illustrates details of the internal reset function logic. Datasheet ® Intel IXP1240 Network Processor 23 ...

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Output Pin RESET_OUT_L ext_rst Soft reset timer rst_in_sync start !zero 140 cycle counter Core clock [31] [30] [29] [28:19] [18] [17] cmd SA PCI sram sdram res arb Core reset reset reset reset reset reset Internal Reset Signals strongarm_rst pci_rst ...

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... If the watchdog timer expires assumed the StrongARM* core has ceased executing instructions properly. The reset generated by the Watchdog Timer will reset each of the functions in the IXP1240. Datasheet ® Intel IXP1240 Network Processor 25 ...

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... Support Miscellaneous Test IEEE 1149.1 SRAM Interface SDRAM Interface Power Supply 26 RESET_OUT_L RESET_IN_L PXTAL CINT_L SCAN_EN TCK_BYP TSTCLK TCK TMS Intel® TDI IXP1240 TDO Network TRST_L Processor NA/SACLK A[18:0] DQ[31:0] CE_L[3:0] SCLK SOE_L SWE_L FWE_L LOW_EN_L HIGH_EN_L MRD_L MCE_L SLOW_EN_L ...

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... P Power supply. Standard open drain allows multiple devices to share as a wire-OR. A pullup is required to OD sustain the inactive state until another agent drives it, and it must be provided by the central resource. Datasheet Intel Description and Table 36 for more information. and Table 36 for more information. ...

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... Intel IXP1240 Network Processor 3.3 Pin Description, Grouped by Function 3.3.1 Processor Support Pins Table 12. Processor Support Pins Processor Support Signal Names PXTAL CINT_L RESET_OUT_L RESET_IN_L Totals: 28 Pin # Type Total Input connection for system oscillator. Typically 3.6864 MHz. Drives internal PLL clock generator. ...

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... J30 J31 K29 L28 K30 K31 L29 M28 L30 L31 M29 N28 M30 M31 I1/ Bidirectional data signals N29 N30 N31 P29 R28 P30 R29 R30 R31 T28 T29 T30 T31 U29 U28 V30 V29 ® Intel IXP1240 Network Processor Pin Descriptions 29 ...

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... Intel IXP1240 Network Processor Table 13. SRAM Interface Pins (Continued) SRAM Interface Signal Names CE_L[3:0] [3] [2] [1] [0] SCLK NA/SACLK SOE_L SWE_L FWE_L LOW_EN_L HIGH_EN_L SLOW_EN_L MCE_L MRD_L Totals: 30 Pin # Type Total A26 SRAM Bus chip enable outputs. Internally decoded from O4 4 B26 SRAM address ...

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... AE2 [46] AE1 [45] U4 [44] V2 [43] U3 [42] U2 [41] U1 [40] T4 [39] T3 [38] T2 [37] T1 [36] R3 [35] R4 [34] P2 [33] P3 [32] N1 [31] N2 [30] N3 [29] M1 [28] M2 [27] N4 [26] M3 Datasheet Intel Type Total O4 15 Multiplexed Row/Column address outputs. I1/ Bidirectional data signals. ® IXP1240 Network Processor Pin Descriptions 31 ...

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... Intel IXP1240 Network Processor Table 14. SDRAM Interface Pins (Continued) SDRAM Interface Pin # Signal Names [25] L1 [24] L2 [23] M4 [22] L3 [21] K1 [20] K3 [19] J1 [18] J2 [17] J3 [16] H1 [15] H2 [14] J4 [13] H3 [12] G1 [11] G2 [10] H4 [9] G3 [8] F1 [7] F2 [6] F3 [5] E1 [4] E2 [3] F4 [2] E3 [1] D1 [0] D2 ...

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... AK24 [33] AL24 [32] AJ23 [31] AK23 Datasheet Intel Type Total IX Bus Clock input. All IX Bus transfers are synchronized to this I3 1 clock. Typical operating frequency 33 MHz - 104 MHz. Port Control outputs. Used to select the transmit and/or receive mode for IX Bus devices, typically MAC devices. ...

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... Intel IXP1240 Network Processor Table 15. IX Bus Interface Pins (Continued) IX Bus Signal Pin # Names [30] AL23 [29] AJ22 [28] AH21 [27] AK22 [26] AL22 [25] AJ21 [24] AH20 [23] AK21 [22] AL21 [21] AJ20 [20] AH19 [19] AK20 [18] AL20 [17] AJ19 [16] AK19 [15] AL19 [14] AJ18 [13] AH17 [12] AK18 [11] AJ17 [10] AK17 [9] AL17 [8] AH16 [7] AJ16 [6] AK16 [5] AL16 ...

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... AL7 SOP AH12 EOP AJ11 Datasheet Intel Type Total In 64-bit Bidirectional IX Bus Mode: • 1-2 MAC mode: Used as an active low flow control enable for MAC 1 (GPIO[0] used as a flow control enable for MAC 0). • 3+ MAC mode: Used in conjunction with RDYCTL_L[3:0]. ...

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... Intel IXP1240 Network Processor Table 15. IX Bus Interface Pins (Continued) IX Bus Signal Pin # Names SOP32 AJ6 EOP32 AL5 TK_OUT AA29 TK_IN AB31 Totals: 36 Type Total Transmit Start Of Packet Indication/Token Request Output. • Output in 32-bit unidirectional IX Bus modes. SOP32 is Transmit Start of Packet output during transmit according to values programmed in the TFIFO control field ...

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... Serial Port (UART) Signal Pin # Names RXD D23 TXD C24 Totals: Datasheet Intel Type Total Bidirectional General Purpose pins. 64-bit Bidirectional IX Bus mode: Accessible by StrongARM* core. Configurable as Input or Output. 32-bit Unidirectional IX Bus mode: Transmit Port Select [2:0] I1/O4 3 outputs. GPIO[3] is sampled during reset to determine if a 32-bit or 16-bit BootROM device is used ...

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... Intel IXP1240 Network Processor 3.3.7 PCI Interface Pins Table 18. PCI Interface Pins PCI Interface Pin # Signal Names AD[31:0] [31] B20 [30] A20 [29] C19 [28] C18 [27] B18 [26] D17 [25] C17 [24] A16 [23] D16 [22] A15 [21] B15 [20] C15 [19] B14 [18] D15 [17] C14 [16] A13 [15] A10 [14] B10 [13] D11 [12] C10 [11] A9 [10] ...

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... A22 PCI_RST_L C21 PCI_CLK D20 A24 PCI_CFN[1:0] C23 Datasheet Intel Type Total Device Select. Indicates that the target has decoded its address I2/O2 the target of the current access. The IXP1240 drives as target STS and receives as initiator. Initialization Device Select. Used as Chip Select during PCI ...

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... Intel IXP1240 Network Processor Table 18. PCI Interface Pins (Continued) PCI Interface Pin # Signal Names GNT_L[0] B21 REQ_L[0] A21 GNT_L[1] C20 REQ_L[1] D19 Totals: 40 Type Total PCI Bus Master Grant 1. Internal PCI arbiter is enabled (PCI_CFN[1:0] = 11): Pin is an output to grant a PCI device 1 control of the PCI Bus. (The ...

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... D29, P1, P31, R1, R2, U30, U31, V1, V31, AH3, AH29, AJ1, AJ2, AJ4, AJ28, AJ30, AJ31, AK1, AK3, AK15, AK29, AK31, AL2, AL3, AL14, AL15, AL18, AL29, AL30 Total VSS pins Total Power Supply Pins Datasheet Intel Type Total P 17 IXP1240 core supply (2V). ...

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... Used for Intel test purposes only. When high, bypasses PLL for I1 1 Test/debug. Must be low for normal system operation. Used for Intel test purposes only. Used as clock input when bypassing the internal PLL clock generator. For Normal I1 1 operation, this pin should not be allowed to float. It should be pulled up or pulled down through the proper value resistor ...

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... Pin Usage Summary Table 22. Pin Usage Summary Type Inputs Outputs Bidirectional Total Signal Power Overall Totals: Datasheet ® Intel IXP1240 Network Processor Quantity 21 68 235 324 108 432 43 ...

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... Intel IXP1240 Network Processor 3.4 Pin/Signal List Table 23. Pin Table in Pin Order Pin Signal Name Number A1 VDDX A2 VSS A3 VSS A4 VSSP1 A5 RESET_OUT_L A6 AD[1] A7 AD[5] A8 AD[8] A9 AD[11] A10 AD[15] A11 PERR_L A12 IRDY_L A13 AD[16] A14 VSS A15 AD[22] A16 AD[24] A17 ...

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... E28 A[15] E29 A[12] E30 A[10] E31 A[9] F1 MDATA[8] F2 MDATA[7] F3 MDATA[6] F4 MDATA[3] F28 A[11] F29 A[8] F30 A[7] Datasheet ® Intel IXP1240 Network Processor Pin Signal Name Number Number F31 A[6] L28 G1 MDATA[12] L29 G2 MDATA[11] L30 G3 MDATA[9] L31 G4 VDDX M1 G28 VDDX M2 ...

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... Intel IXP1240 Network Processor Table 23. Pin Table in Pin Order (Continued) Pin Signal Name Number T2 MDATA[38] T3 MDATA[39] T4 MDATA[40] T28 DQ[7] T29 DQ[6] T30 DQ[5] T31 DQ[4] U1 MDATA[41] U2 MDATA[42] U3 MDATA[43] U4 MDATA[45] U28 DQ[2] U29 DQ[3] U30 VSS U31 VSS V1 VSS V2 MDATA[44] V4 VDDX ...

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... FDAT[1] AJ15 FDAT[4] AJ16 FDAT[7] AJ17 FDAT[11] AJ18 FDAT[14] AJ19 FDAT[17] AJ20 FDAT[21] AJ21 FDAT[25] AJ22 FDAT[29] Datasheet ® Intel IXP1240 Network Processor Pin Signal Name Number Number AJ23 FDAT[32] AK28 AJ24 FDAT[36] AK29 AJ25 FDAT[40] AK30 AJ26 FDAT[43] AK31 AJ27 ...

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... Intel IXP1240 Network Processor 3.5 Signals Listed in Alphabetical Order Table 24. Pin Table in Alphabetical Order Signal Name A[0] A[1] A[10] A[11] A[12] A[13] A[14] A[15] A[16] A[17] A[18] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] AD[0] AD[1] AD[10] AD[11] AD[12] ...

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... FDAT[2] FDAT[20] FDAT[21] FDAT[22] FDAT[23] FDAT[24] FDAT[25] FDAT[26] FDAT[27] FDAT[28] FDAT[29] FDAT[3] FDAT[30] FDAT[31] FDAT[32] FDAT[33] FDAT[34] FDAT[35] FDAT[36] Datasheet Intel Pin Pin Signal Name Number Number AH13 FDAT[37] AL25 AK12 FDAT[38] AK25 AL12 FDAT[39] AH24 AJ13 FDAT[4] AJ15 AK13 FDAT[40] ...

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... Intel IXP1240 Network Processor Table 24. Pin Table in Alphabetical Order (Continued) Signal Name MDATA[18] MDATA[19] MDATA[2] MDATA[20] MDATA[21] MDATA[22] MDATA[23] MDATA[24] MDATA[25] MDATA[26] MDATA[27] MDATA[28] MDATA[29] MDATA[3] MDATA[30] MDATA[31] MDATA[32] MDATA[33] MDATA[34] MDATA[35] MDATA[36] MDATA[37] MDATA[38] MDATA[39] MDATA[4] MDATA[40] MDATA[41] MDATA[42] ...

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... VDDP1 VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX Datasheet Intel Pin Pin Signal Name Number Number B19 VDDX P28 B27 VDDX V4 H31 VDDX V28 J29 VDDX AB4 K2 VDDX AB28 ...

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... Figure 7 through Figure 11 to one or more MAC devices and is accompanied by a pin description for the IX Bus in that mode. Figure 7. 64-Bit Bidirectional IX Bus, 1-2 MAC Mode ® Intel IXP1240 Processor RDYCTL_L[4:0] PORTCTL_L[3:0] 52 illustrate the four IX Bus modes. Each figure shows the logic interface ...

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... FPS[2:0] FDAT[63:0] FBE_L[7:0] SOP EOP TXAXIS RxFAIL 3.3V SOP32 not used EOP32 ® Intel IXP1240 Network Processor Dual Fast Port Device CINT_L[1:0] ® (Intel IXF1002) [1:0] FLCT[1:0] FLCT_LAT [1:0] TxRDY[1:0] TxCTL_L RxRDY[1:0] RxCTL_L RxSEL_L TxSEL_L FPS FDAT[63:0] FBE_L[7:0] SOP EOP TXAXIS ...

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... Intel IXP1240 Network Processor Table 25. 64-Bit Bidirectional IX Bus, 1-2 MAC Mode Signal GPIO[3:1] GPIO[0 RDYCTL_L[3:0] RDYCTL_L[4] RDYBUS[7:0] PORTCTL_L[3:0] FPS[2:0] SOP SOP32 EOP EOP32 TK_IN TK_OUT RXFAIL TXASIS FBE_L[7:0] FDAT[63:0] FAST_RX1 FAST_RX2 54 Description Active High, input/output assigned to StrongARM* core not used for MAC interface. ...

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... RDYBUS[7:0] [31:0] RDYCTL_L[4:0] 5 > 32 FCLK [15:0] PORTCTL_L[3:0] 4 > 16 FCLK FPS[2:0] FDAT[63:0] FBE_L[7:0] SOP EOP TXAXIS RxFAIL not used SOP32 EOP32 3.3V ® Intel IXP1240 Network Processor 3.3V MAC0 wireor CINT[7: FLCTL[7:0] [19] e FCLK RxRDY[7:0] TxRDY[7:0] [27] RxCTL_L [23] TxCTL_L [1] RxSEL_L [0] TxSEL_L FPS[2:0] ...

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... Intel IXP1240 Network Processor Table 26. 64-Bit Bidirectional IX Bus, 3+ MAC Mode (Shared IX Bus Operation Only in This Mode) Signal GPIO[3:1] GPIO[0] RDYCTL_L[4:0] RDYBUS[7:0] PORTCTL_L[3:0] FPS[2:0] SOP SOP32 EOP EOP32 TK_IN TK_OUT RXFAIL TXASIS FBE_L[7:0] 56 Description Active High input/output assigned to StrongARM* core not used for MAC interface. ...

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... TXASIS RXFAIL SOP EOP Datasheet Intel Description Active High, read and write data. Tri-stated in shared IX Bus mode when the IXP1240 does not own the IX Bus. Active High ready input from FastPort 0, pulldown 10 KOhms to GND if not used. Active High ready input from FastPort 1, pulldown 10 KOhms to GND if not used. ...

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... Intel IXP1240 Network Processor Figure 10. 32-Bit Unidirectional IX Bus, 1-2 MAC Mode ® Intel IXP1240 Processor Receive Transmit 58 CINT_L GPIO[0] RDYBUS[7:0] [0] RDYCTL_L[4:0] [1] [0] PORTCTL_L[1:0] FDAT [31:0] FBE_L[3:0] FPS[2:0] RxFAIL SOP EOP [2] PORTCTL_L[3:2] FDAT[63:32] FBE_L[7:4] GPIO[3:1] TXAXIS SOP32 EOP32 [4] [2] [3] [1] [3] 3.3V ...

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... RDYCTL_L[3:0] RDYBUS[7:0] TK_IN TK_OUT FAST_RX1 FAST_RX2 Datasheet Intel Description Active high outputs, Transmit Port Select [2:0]. Active Low, output. Transmit Device Selects [1:0]. Active High, output, transmit Start of Packet. SOP32 is output during transmit according to value programmed in the TFIFO control field. Active High, output, transmit End of Packet. EOP32 is output during transmit according to value programmed in the TFIFO control field ...

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... Intel IXP1240 Network Processor Figure 11. 32-bit Unidirectional IX Bus, 3+ MAC Mode (3-4 MACs Supported) ® Intel IXP1240 Processor Receive Transmit 60 CINT_L[0] [15:0] 4 > 16 RDYCTL_L[3:0] decoder FCLK RDYBUS[7:0] 2 > 4 decoder RDYCTL_L[4] [3:0] e [0] Q PORTCTL_L[1:0] D FCLK FDAT [31:0] FBE_L[3:0] FPS[2:0] RxFAIL SOP EOP 2 > ...

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... RDYCTL_L[3:0] RDYBUS[7:0] TK_IN TK_OUT FAST_RX1 FAST_RX2 Datasheet Intel Description Active high outputs, Transmit Port Selects [2:0]. Active Low, outputs. Used with GPIO[0]/FC_EN0_L/TXPEN for transmit device select via external 2-to-4 decoder. Active High, output, transmit enable. Used with PORTCTL_L[3:2] for transmit device select via external 2-to-4 decoder ...

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... Intel IXP1240 Network Processor 3.7 IX Bus Decode Table Listed by Operating Mode Type Table 29. IX Bus Decode Table Listed by Operating Mode Type PIN NAME Bidirectional 1-2 1110 MAC0 RxSEL 1101 MAC1 RxSEL PORTCTL_L[3:0 1011 MAC0 TxSEL ] 0111 MAC1 TxSEL 1111 No Select ...

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... MAC6 Rx 00111 MAC4 Tx 00110 MAC5 Tx 00101 MAC6 Tx 00011 MAC4 Flw Ctl enable 00010 MAC5 Flw Ctl enable 00001 MAC6 Flw Ctl enable ® Intel IXP1240 Network Processor 32-bit 32-bit Unidirectional 1-2 Unidirectional 3+ MAC mode MAC mode Tx EOP Tx EOP MAC1 Flw Ctl ...

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... Intel IXP1240 Network Processor 3.8 Pin State During Reset Table 30 summarizes IXP1240 pin states during reset. Table 30. Pin State During Reset Function SRAM SCLK SRAM A[17:0] SRAM DQ[31:0] SRAM CE_L[3:0] SRAM SLOW_EN_L SRAM SOE_L SRAM SWE_L SRAM HIGH_EN_L SRAM LOW_EN_L ...

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... RXFAIL IX Bus TK_IN IX Bus TK_OUT IX Bus GPIO[3] IX Bus GPIO[2] IX Bus GPIO[1] IX Bus GPIO[0] Misc Test TCK_BYP Datasheet Intel Pin Name Pin Reset State Hi-Z PCI_CFN[1:0]=00, PCI_RST=Hi-Z PCI_CFN[1:0]=11, PCI_RST=output, low Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z PCI_CFN[1:0]=00, GNT_L[1:0]=Hi-Z PCI_CFN[1:0]=11, GNT_L[1:0]=output, high ...

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... Intel IXP1240 Network Processor Table 30. Pin State During Reset (Continued) Function Misc Test TSTCLK Misc Test SCAN_EN Processor PXTAL Support Processor CINT_L Support Processor RESET_IN_L Support Processor RESET_OUT_L Support Serial RXD Serial TXD IEEE 1149.1 TCK IEEE 1149.1 TDI IEEE 1149.1 TDO IEEE 1149 ...

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... V delta Datasheet Table 31 lists the absolute maximum ratings for the Parameter Minimum --- j 1.9 V 3.0 V -55°C 0.0 V ® Intel IXP1240 Network Processor ) of 232 MHz at a junction core (Table 31) is not ) must not be delta Maximum Comment 100°C 3 supply 3.6 V 3.3 V supply 125° ...

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... Intel IXP1240 Network Processor The power specifications listed below are based on the following assumption: • PCI Bus Frequency (PCI_CLK MHz. Table 32. Functional Operating Range Parameter Operating temperature range Supply voltage (core and PLL), VDD, VDDP1 Supply voltage (I/O), VDDX, VDDREF Table 33 ...

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... Note: Refer to the IXP1200 Network Processor Heatsinks: ja and Airflow - Application Note for additional information on heatsinks and thermal management. Datasheet 100 200 300 400 Airflow (LFM) ® Intel IXP1240 Network Processor Bare Package HST353 HST354 HST355 Fan HS 500 600 700 800 ...

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... Intel IXP1240 Network Processor 4.2 DC Specifications The IXP1240 supports two fundamental I/O buffer Types: Type 1 and Type 2. The Pin Description section defines which pins use which I/O buffer type. The driver characteristics are described in the following sections. Please note that IXP1240 input pins are not 5 V tolerant. Devices driving the IXP1240 must provide 3 ...

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... Undershoot Overshoot -0.75 V VDDX + 0.7 V -0.7 V VDDX + 0.65 V -0.7 V VDDX + 0.6 V -0.75 V VDDX + 1.0 V -0.7 V VDDX + 0.65 V ® Intel IXP1240 Network Processor Minimum Maximum 0.5 x VDDX VDD_REF + 0.5 V --- 0.3 x VDDX 0.9 x VDDX --- --- 0.1 x VDDX - ...

Page 72

... Intel IXP1240 Network Processor 4.3 AC Specifications 4.3.1 Clock Timing Specifications The ac specifications consist of input requirements and output responses. The input requirements consist of setup and hold times, pulse widths, and high and low times. Output responses are delays from clock to signal. The ac specifications are defined separately for each clock domain within the IXP1240 ...

Page 73

... Volts < 40%-60% T cyc T high low Parameter Minimum PCI_CLK cycle time 15 PCI_CLK high time 6 PCI_CLK low time PCI_CLK slew rate 1.5 F /PCI Clock Ratio 2:1 core ® Intel IXP1240 Network Processor A8554-01 Maximum Unit ns --- ns --- ns 4 V/ns 73 ...

Page 74

... Intel IXP1240 Network Processor Table 40. 33 MHz PCI Clock Signal AC Parameters Symbol T cyc T high T low 1. 0.2 VDDX to 0.6 VDDX. 2. Not tested. Guaranteed by design. Figure 15. PCI Bus Signals PCI_CLK Outputs Inputs Note 0.4 VDDX for 3.3 volt PCI signals test 74 Parameter ...

Page 75

... These parameters are at variance with those in the PCI Local Bus Specification, Revision 2.2. 2. Point-to-point signals are REQ_L, GNT_L. 3. Not tested. Guaranteed by design. 4. Bused signals are AD, CBE_L, PAR, PERR_L, SERR_L, FRAME_L, IRDY_L, TRDY_L, DEVSEL_L, STOP_L. Datasheet Intel Parameter Minimum 1.5 1.5 2 ...

Page 76

... TK_OUT hi-z to valid output. OETK 1. core_clk is nominally running at 29.491 MHz after a hard reset when PXTAL is 3.6864 MHz. Figure 16. RESET_IN_L Timing Diagram VDD: VDDX, VDDP, VDD_REF RESET_IN_L sram_rst_1 [note 1] GPIO<3> TK_OUT Note 1: Internal signal to the Intel® IXP1240 processor. 76 Parameter Minimum 150 RST Maximum ...

Page 77

... Caution: A clock signal must be applied to the core of the IXP1240 when using IEEE 1149.1 functions. The PXTAL clock input should be active, or, if using bypass mode, (TCK_BYP = 1) TSTCLK should be active. Failure to observe this rule may cause device damage. Datasheet ® Intel IXP1240 Network Processor 77 ...

Page 78

... Intel IXP1240 Network Processor 4.3.6.1 IEEE 1149.1 Timing Specifications Figure 17. IEEE 1149.1/Boundary-Scan General Timing 78 Tbscl tck tms, tdi Tbsis Tbsih tdo Tbsoh Tbsod Data In Tbsss Tbssh Data Out Tbsdh Tbsdd Tbsch A8557-01 Datasheet ...

Page 79

... Tbsoe Tbsde Parameter Minimum Typical 10 – 50 – – 40 – 20 – 40 – 40 – 20 – 5 – 5 – 40 – ® Intel IXP1240 Network Processor Tbsoz Tbsdz A8558-01 Maximum Units Notes MHz – – – ns – – ns – – – ns – – ns – – ...

Page 80

... Intel IXP1240 Network Processor 4.3.7 IX Bus 4.3.7.1 FCLK Signal AC Parameter Measurements Figure 19. FCLK Signal AC Parameter Measurements V Table 44. FCLK Signal AC Parameter Measurements Symbol F CLK high 2 T low V ptp Maximum F frequency for 232 MHz rated parts is 104 MHz. Maximum F CLK Maximum F frequency for 166 MHz rated parts is 66 MHz. ...

Page 81

... Table 46. ® Intel IXP1240 Network Processor T val(min) T off T h A8559-01 Maximum (IX Bus Speed) Unit Condition 104 66 85 104 MHz MHz MHz 7.0 7.0 5. load --- --- ...

Page 82

... Intel IXP1240 Network Processor Table 46. Signal Delay Derating Signal FDATA[63:0] 0.055 FBE_L[7:0] 0.055 FPS[2:0] 0.065 TK_REQ_OUT 0.065 TK_REQ_IN 0.065 RDYCTL_L[4:0] 0.065 RDYBUS[7:0] 0.065 TXAXIS 0.065 EOP 0.065 SOP 0.065 GPIO[3:0] 0.065 PORTCTL_L[3:0] 0.095 TK_OUT 0.095 RXFAIL 0.095 82 Maximum Derating (ns/pF) ...

Page 83

... FBE_L[7:0] int_1240_OE Notes: int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. Status Data Transfer indicated with RaS, RbS, RcS, etc. ...

Page 84

... Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1250_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP/SOP_RX, EOP/EOP_RX, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 85

... Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 86

... Intel IXP1240 Network Processor Figure 24. 64-Bit Bidirectional IX Bus Timing - Consecutive Receive and Transmit, EOP on 7th Data Return with Status VDD: VDDX, VDDP, VDD_REF RESET_IN_L sram_rst_1 [note 1] GPIO<3> TK_OUT Note 1: Internal signal to the Intel® IXP1240 processor RST 509 PXTAL Cycles Valid ...

Page 87

... Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 88

... Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 89

... Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 90

... Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE#x, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 91

... Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 92

... Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not anIntel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 93

... Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 94

... Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 95

... Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 96

... Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 97

... Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 98

... Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 99

... Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 100

... SOP EOP FBE_L[3:0] Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. No Sel No Sel MAC2/Rx B ...

Page 101

FCLK No Sel No Sel PORTCTL_L[1:0] MAC0/Rx A MAC1/ used with PORTCTL_L 3+ MAC mode only ) RDYCTL_L[4] ext_MAC0_Rx_L ext_MAC1_Rx_L ext_MAC2_Rx_L ext_MAC3_Rx_L Port A Port B FPS[2: FDAT[31:0] Ra0 Ra1 Rb0 Rb1 ...

Page 102

... SOP EOP FBE_L[3:0] Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. No Sel No Sel MAC2/Rx C ...

Page 103

... SOP EOP FBE_L[3:0] Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins Sel No Sel MAC2/Rx C ...

Page 104

FCLK No Sel No Sel PORTCTL_L[1:0] MAC0/Rx A MAC1/ used with PORTCTL_L 3+ MAC mode only ) RDYCTL_L[4] ext_MAC0_Rx_L ext_MAC1_Rx_L ext_MAC2_Rx_L ext_MAC3_Rx_L FPS[2:0] Port A Ra FDAT[31:0] Ra0 Ra1 Ra2 RaS Rb0 Rb1 Rb2 12 SOP EOP FBE_L[3:0] ...

Page 105

FCLK No PORTCTL_L[1:0] MAC0/Rx A MAC0/Rx B Sel ( used with PORTCTL_L 3+ MAC mode only ) RDYCTL_L[4] ext_MAC0_Rx_L ext_MAC1_Rx_L ext_MAC2_Rx_L ext_MAC3_Rx_L Port A FPS[2: FDAT[31:0] Ra1 Rb0 Rb1 Ra0 SOP EOP FBE_L[3:0] Notes: ...

Page 106

FCLK No No PORTCTL_L[1:0] MAC0/Rx A MAC1/Rx B Sel Sel ( used with PORTCTL_L RDYCTL_L[4] 3+ MAC mode only ) ext_MAC0_Rx_L ext_MAC1_Rx_L ext_MAC2_Rx_L ext_MAC3_Rx_L FPS[2:0] Port A Port FDAT[31:0] Ra0 Ra1 Rb0 Rb1 ...

Page 107

FCLK No Sel No Sel PORTCTL_L[3:2] MAC0/Tx A GPIO[0] ( used with PORTCTL_L 3+ MAC mode only ) ext_MAC0_Tx_L ext_MAC1_Tx_L ext_MAC2_Tx_L Port A GPIO[3:1] FDAT[31:0] Ta0 Ta1 Ta2 Ta3 Ta15 SOP32 EOP32 FBE_L[7:4] Notes: Signals using prefix "ext_" are outputs ...

Page 108

FCLK No Sel PORTCTL_L[3:2] MAC0/Tx A GPIO[0] ( used with PORTCTL_L 3+ MAC mode only ) ext_MAC0_Tx_L ext_MAC1_Tx_L ext_MAC2_Tx_L Port A GPIO[3:1] TaP TaP FDAT[31:0] Ta0 Ta1 Ta2 Ta14 Ta15 0 1 SOP32 EOP32 FBE_L[7:4] Notes: Signals using prefix "ext_" ...

Page 109

... FP_READY_WAIT=0 FAST_RX1 int_1240_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. Intel® IXP1240 Processor int_1240_OE is not an SOP, EOP, TXAXIS, SOP32, EOP32 pins. the IXP1240 drives the FDATx, FBE_Lx, Status Command indicated with STS-A, STS-B, etc. ...

Page 110

... Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 111

... Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 Status Command indicated with STS-A, STS-B, etc. ...

Page 112

... Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx,SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 113

... FAST_RX1 int_1240_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel IXP1240 Processor signal shown to indicate when the IXP1240 drives the ® FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 114

... FAST_RX1 int_1240_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel IXP1240 Processor signal shown to indicate when the IXP1240 drives the ® FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 115

... FAST_RX2 int_1240_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, ® FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 116

... FAST_RX2 int_1240_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1240_OE is not an Intel ® IXP1240 Processor signal shown to indicate when the IXP1240 drives the FDATx, FBE_Lx, SOP, EOP, TXAXIS, SOP32, EOP32 pins. Status Command indicated with STS-A, STS-B, etc. ...

Page 117

... Figure 56. Consecutive Fetch Ready Flags, 3+ MAC Mode (with External Decoder) - RDYBUS_TEMPLATE_CTL[10]=0 FCLK RDYCTL_L[4:0] NOP ext_MAC0_RxSel_L ext_MAC1_RxSel_L ext_MAC2_RxSel_L ext_MAC3_RxSel_L RDYBUS[7:0] Note: Signals using prefix "ext_" are outputs of an external decoder. Datasheet Intel MAC0/ RxRdy MAC0/ TxRdy MAC1/ TxRdy MAC0/TxRdy Flags MAC1/TxRdy Flags MAC0/RxRdy NOP MAC1/RxRdy ...

Page 118

... Intel IXP1240 Network Processor Figure 57. Fetch Ready Flags, Get/Send Commands, 3+ MAC Mode (with External Registered Decoder) - RDYBUS_TEMPLATE_CTL[10]=0 FCLK MAC0/TxRdy RDYCTL_L[3:0] NOP ext_MAC0_TxRdy_L RDYBUS[7:0] Note: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. Figure 58. Ready Bus Control Timing, Fetch Ready Flags - Flow Control - Fetch Ready Flags, ...

Page 119

... Configuration uses an external Flow Control latch, and an external registered decoder. Signals using prefix "ext_" are outputs of the external registered decoder. Datasheet RxRdyMAC0 RxRdyMAC1 RxRdyMAC2 NOP NOP NOP MAC0/RxRdy Flags MAC1/RxRdy Flags ® Intel IXP1240 Network Processor FlwCtMAC0 NOP NOP MAC2/RxRdy Flags MAC0/Flow Control Mask A8606-01 119 ...

Page 120

... TK_OUT _L1 (is TK_IN to _L2 ) TK_OUT _L2 FDAT[63:0] PORTCTL_L[7:0] Notes Driven by the Intel if the transfer Driven high for one cycle by the IXP1200 Network Processor _L2 (no port is selected), then tristated Weak external pull-up resistors are recommended on PORTCTL_L[7:0], FPS[2:0] and TXAXIS. 4.3.8 SRAM Interface 4 ...

Page 121

... MHz MHz MHz — — — 8.62 4.02 4 3.3 4.02 4 3.3 0.29 0.25 0.21 ® Intel IXP1240 Network Processor Maximum (IXP1240 Core Speed) Unit 166 200 232 MHz MHz MHz 83 100 116 MHz — — — ns — — — ...

Page 122

... Intel IXP1240 Network Processor 4.3.8.2 SRAM Bus Signal Timing Figure 62. SRAM Bus Signal Timing SCLK Outputs Inputs Table 48. SRAM Bus Signal Timing Symbol T Clock to data output valid delay val T Clock to control outputs valid delay ctl Data input setup time before NA/SACLK ...

Page 123

... Intel IXP1240 Network Processor Minimum Derating (ns/pF) (IX Bus Speed) 100 MHz 116 MHz — — 0.025 0.015 0.025 0.015 0.025 0.015 0.025 0.015 0.025 ...

Page 124

... Intel IXP1240 Network Processor 4.3.8.3 SRAM Bus - SRAM Signal Protocol and Timing Figure 63. Pipelined SRAM Read Burst of Eight Longwords SCLK SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L CE_L[3:0] A[18:0] SWE_L SOE_L DQ[31:0] 124 CE_L<3:0> = 1110 D(A0) D(A1) D(A2) D(A3) D(A4) D(A5) D(A6) ...

Page 125

... Figure 64. Pipelined SRAM Write Burst of Eight Longwords SCLK SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L CE_L[3:0] A[18:0] SWE_L SOE_L DQ[31:0] Datasheet ® Intel IXP1240 Network Processor CE_L<3:0> = 1110 D(A0) D(A1) D(A2) D(A3) D(A4) D(A5) D(A6) D(A7) A8611-01 125 ...

Page 126

... Intel IXP1240 Network Processor Figure 65. Pipelined SRAM Read Burst of Four From Bank 0 Followed by Write Burst of Four From Bank 8 SCLK SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L CE_L[3:0] A[18:0] SWE_L SOE_L DQ[31:0] Note 1: There is always a 1 clock cycle idle state on the data bus when switching from read to write. ...

Page 127

... SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L CE_L[3:0] A[18:0] SWE_L SOE_L DQ[31:0] Note 1: There is always a one clock cycle idle state on the data bus when switched from a read to write cycle. Datasheet ® Intel CE_L<3:0> = 1110 D(A1) D(A2) D(A3) D(A0) Idle State [note 1] IXP1240 Network Processor CE_L< ...

Page 128

... Intel IXP1240 Network Processor Figure 67. Flowthrough SRAM Read Burst of Eight Longwords SACLK SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L CE_L[3:0] A[18:0] SWE_L SOE_L DQ[31:0] 128 CE_L<3:0> = 1110 D(A0) D(A1) D(A2) D(A3) D(A4) D(A5) D(A6) A7 D(A7) A8614-01 Datasheet ...

Page 129

... SRAM SlowPort Cycle Count (Does not apply to BootROM) BootROM Cycle Count (11) Cycle time = Cycle Count + 1 (12 cycles) 15:8 7 SLOW__EN_L Deassert. (3) SLOW__EN_L Assert (10) SLOW_RD_L/SLOW_WE_L Deassert. (5) ® Intel IXP1240 Network Processor Valid Address Valid Valid SLOW_EN_L Deassert. (3) SLOW_RD_L Deassert. (5) ...

Page 130

... Intel IXP1240 Network Processor Figure 69. BootROM Write A[18:0] DQ[31:0] SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L CE_L[3:0] Externally Generated Signal BootROM Chip select signal SLOW_EN_L or CE_L<3:0> Cycle Count = Example for the following setting in SRAM registers SRAM_SLOW_CONFIG 31:16 RES SRAM_BOOT_CONFIG 31:24 23: SLOW_RD_L/SLOW_WE_L Assert. (9) ...

Page 131

... Figure 70. Pipelined SRAM Two Longword Burst Read Followed by BootROM Write SCLK A[18:0] DQ[31:0] Buffered DQ[31:0] SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L CE_L[3:0] SWE_L SOE_L BootROM_CE_L[3:0] Datasheet Intel A2 A1 D(A1) D(A1) D(A2) CE_L<3:0> = 1110 BootROM_CE_L = -(-SLOW_EN_L & -CE_L) ® IXP1240 Network Processor A3 A3 D(A3) D(A3) D(A3) ...

Page 132

... Intel IXP1240 Network Processor 4.3.8.6 SRAM Bus - Slow-Port Device Signal Protocol and Timing Figure 71. SRAM SlowPort Read DQ[31:0] SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L MCE_L Externally Generated Signal SRAM SlowPort Chip select signal - MCE_L & address Cycle Count = Example for the following setting in SRAM registers ...

Page 133

... SRAM SlowPort Cycle Count (11) Cycle time = Cycle Count + 1 (12 cycles) BootROM Cycle Count (Does not apply to SRAM SlowPort) 15:8 7 SLOW__EN_L Deassert. (3) SLOW_RD_L/SLOW_WE_L Deassert. (5) SLOW__EN_L Assert (10) ® Intel IXP1240 Network Processor Valid Address Valid Data SLOW_EN_L Deassert. (3) SLOW_RD_L Deassert. (5) ...

Page 134

... Intel IXP1240 Network Processor Figure 73. SRAM SlowPort SCLK A[18:0] DQ[31:0] SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L MCE_L ext_CE_L (MCE_L.AND.Ax) Cycle_count Register Settings used for these timings: SRAM_SLOW_CONFIG=000A:0B0Fh where RDY_L Pause State=Ah, BCC=0Bh, and SCC=0Fh SRAM_SLOWPORT_CONFIG=0D0E:0501h where SRWA=0Dh, SCEA=0Eh, SRWD=05h, SCED=01 SRAM_CSR=0009:4810h where <19>=1, RDY_L enabled ...

Page 135

... Figure 74. Pipelined SRAM Two Longword Burst Read Followed By SlowPort Write SCLK A[18:0] DQ[31:0] Buffered DQ[31:0] MCE_L SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L CE_L[3:0] SWE_L SOE_L BootROM_CE_L[3:0] Datasheet ® Intel IXP1240 Network Processor D(A1) D(A2) D(A3) CE_L<3:0> = 1110 A3 D(A3) D(A3) D(A3) A8621-01 135 ...

Page 136

... Intel IXP1240 Network Processor 4.3.9 SDRAM Interface 4.3.9.1 SDCLK AC Parameter Measurements Figure 75. SDCLK AC Timing Diagram Vt1 = 0.5*VDDX Vt2 = 0.4*VDDX Vt3 = 0.3*VDDX Table 50. SDCLK AC Parameter Measurements Symbol Freq Clock frequency T Cycle time cyc T Clock high time high T Clock low time low ...

Page 137

... Table 52. (min) parameters are tested under 0 pF load best case conditions (Vdd=2.1, ctl , the T timings are both what the tester must measure and what the sup su ® Intel IXP1240 Network Processor T val(min) T off ctl(min) A8905-01 Maximum (IXP1240 Core Speed) ...

Page 138

... Intel IXP1240 Network Processor Table 52. Signal Delay Deratings for T Signal 83 MHz SDCLK 0.053 DQM 0.065 WE_L 0.065 RAS_L 0.065 CAS_L 0.065 MADR[14:0] 0.065 MDATA[63:0] 0.095 4.3.9.3 SDRAM Signal Protocol This section describes the SDRAM timing parameters referenced in the SDRAM timing diagrams that follow ...

Page 139

... Most PC100 type SDRAM devices allow a zero-delay read-write turnaround. However, tHZmax for PC100 devices is 5.4ns (CASL= (CASL=3) and tON for the IXP1240 clock tRWT would be required to avoid bus contention. Datasheet ® Intel IXP1240 Network Processor 139 ...

Page 140

... Intel IXP1240 Network Processor Figure 77. SDRAM Initialization Sequence SDCLK RAS_L CAS_L WE_L MADR MDAT DQM Notes: 1. Number of total initialization phase refresh cycles programmed as INIT_RFRSH value in register SDRAM_MEMINIT. 2. Burst length and CAS latency values programmed as BURSTL value in register SDRAM_MEMCTL0 emitted in this cycle. ...

Page 141

... SDCLK RAS_L CAS_L WE_L MADR MDAT DQM Notes: 1. Parameters tRWT, tDPL, tDQZ, tRC, tRRD, tRCD, tRASmin, and tRP programmed into register SDRAM_MEMCTL1 2. CAS Latency value (CASL programmed in SDRAM_MEMCTL0 Datasheet Intel tRASmin tRCD Precharge Read command Activate command command (terminates access) ® ...

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... Intel IXP1240 Network Processor Figure 79. SDRAM Write Cycle SDCLK RAS_L CAS_L WE_L MADR MDAT DQM Notes: 1. Parameters tRWT, tDPL, tDQZ, tRC, tRRD, tRCD, tRASmin, and tRP programmed into register SDRAM_MEMCTL1 2. CAS Latency value (CASL programmed in SDRAM_MEMCTL0 142 tRASmin tRCD tDPL ...

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... Are asynchronous relative to any device outside the IXP1240. Datasheet tRASmin tRCD tDQZ DQM remains high Activate Read during modify command command ® Intel IXP1240 Network Processor tDPL tRWT Write DQM remains high command until next read or write command Precharge command A8627-01 ...

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... Mechanical Specifications 5.1 Package Dimensions The IXP1240 is contained in a 432-HL-PBGA package, as shown in the following illustrations. Figure 81. IXP1240 Part Marking Pin 1 144 i GCIXP1240xx FFFFFFFF INTEL M C 2001 xxxxxxxSz YWW PHILLIPPINES Name FPO # Intel Legal BSMC (ALT# & DATE CODE, COO) A8906-02 Datasheet ...

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... Figure 82. 432-Pin HL-PBGA Package - Bottom View 0. Figure 83. IXP1240 Side View Figure 84. IXP1240 A-A Section View Datasheet ® Intel IXP1240 Network Processor A 1 Ball Corner A7063-02 bbb C ccc aaa –C– Seating Plane A7064-01 P ddd A7043-01 145 ...

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... Intel IXP1240 Network Processor 5.2 IXP1240 Package Dimensions (mm) Table 53. IXP1240 Package Dimensions (mm) Symbol A Overall thickness A Ball height 1 A Body thickness 2 D Body size D Ball footprint 1 E Body size E Ball footprint 1 b Ball diameter aaa Coplanarity bbb Parallel ccc Top flatness ...