GCIXP1240AC Intel, GCIXP1240AC Datasheet - Page 19

• Manufacturer Part Number: GCIXP1240AC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1240AC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 837152

Status:
20.
Problem:
Implication:
Workaround:
Status:
21.
Problem:
Implication:
Workaround:
Status:
Specification Update
except the ordered queue. This queue allocation is not a requirement, only a recommendation for
possible performance implications. No additional cycles are inserted in this workaround if the
instruction sequences are valid program design goals.
NoFix
Read-Lock CAM Operations from the StrongARM* Core to SRAM
StrongARM* core instructions that use the SRAM CAM address range (0x1200 0000 - 0x127F
FFFF) to perform a read-locked access can not rely on the lock attempt succeeding.
StrongARM* applications that share data structures with the Microengines cannot rely on the
SRAM CAM to provide atomic access to those data structures. When a StrongARM* application
issues a read_lock operation, the operation may be placed in the read_lock fail queue by the SRAM
controller. The application determines whether or not the operation was placed in the read_lock fail
queue by checking the value of the RLS bit of the SRAM_CSR register. To determine when a
failed read_lock request is eventually moved from the read_lock rail queue to the CAM, the
application polls the SRAM_CSR register until the RLRS bit is set to 1. The SRAM controller is
incorrectly failing to set the RLRS bit when read_lock operation is moved from the read_lock fail
queue to the SRAM CAM. Therefore, a StrongARM* application is not notified when a read_lock
request is ultimately granted. This will cause locks to be placed in the CAM without application
awareness.
None. If a mutual exclusion mechanism is required, the following approaches may be used in place
of the SRAM CAM:
NoFix
66 MHz Capable Bit
The IXP1240 is 66 MHz capable, but the 66 MHz Capable Bit (bit 21) in the PCI_CMD_STAT
register is incorrectly fixed to zero indicating that it is not capable of 66 MHz operation.
When this bit is read, the IXP1240 incorrectly indicates that it is not capable of operating at 66
MHz as defined in the PCI Local Bus Specification, Revision 2.2.
Do not use this bit for determining the maximum operating frequency of the IXP1240’s PCI bus.
NoFix.
1. Use the SRAM Bit Test & Set and Bit Test & Clear atomic operations (refer to Errata 32).
2. Create a Microengine service thread that will access the SRAM CAM on behalf of the
StrongARM* application. For information on building a service thread that is callable from the
StrongARM* core refer to the description of the SHRIMP API and Dispatch Library in the
IXP1200 Network Processor Family Microcode Software Reference Manual.
Intel
®
IXP1240 Network Processor
Errata
19